The ADS8341 is a 4-channel, 16-bit sampling analog-to-digital (A/D) converter with a synchronous serial interface. Typical power consumption is 8mW rate and +5V supply at 100kHz throughput. The reference voltage (VREF) can be varied between 500mV and VCC, providing a corresponding input voltage range of 0V to VREF. The device includes a shutdown mode that reduces power consumption to less than 15µW. The ADS8341 operates down to 2.7V. The low power consumption, high speed and on-board multiplexer ADS8341 are ideal for battery powered systems such as personal digital assistants, portable multi-channel data loggers and measurement equipment. The serial interface also provides low-cost isolation for remote data acquisition. The ADS8341 is available in an SSOP-16 package and operates over the -40°C to +85°C temperature range.

feature

PIN code and PIN code of ADS7841

Single Supply: 2.7V to 5V

4-channel single-ended or

2-channel differential input

Up to 100kHz conversion rate

86dB SINAD

serial interface

SSOP-16 Packaging

application

data collection

Test and Measurement

Industrial Process Control

personal digital assistant

battery powered system

PIN configuration diagram

PIN name description

1 + VCC supply, 2.7V to 5V

2 CH0 analog input channel 0

3 CH1 analog input channel 1

4 CH2 analog input channel 2

5 CH3 analog input channel 3

6 COM Ground Reference for Analog Inputs. Sets the zero-code voltage in single-ended mode. Connect this pin to ground or reference.

7 SHDN shutdown. When low, the device enters a very low power shutdown mode.

8 VREF Voltage Reference Input. See the Electrical Characteristics table for ranges.

9 + VCC supply, 2.7V to 5V

10 GND Ground. Connect to analog ground

11 GND Ground. Connect to analog ground.

12 DOUT Serial Data Output. Data is shifted on the falling edge of DCLK. When CS is high, this output is high impedance.

13 BUSY busy output. When CS is high, this output is high impedance.

14 DIN Serial Data Input. If CS is low, data is latched on the rising edge of DCLK.

15 CS Chip Select Input. Controls conversion timing and enables serial input/output registers.

16 DCLK external clock inputs. This clock runs the SAR conversion process and synchronizes serial data I/O. Maximum input clock frequency

Equal to 2.4MHz, achieving a 100kHz sampling rate.

Theory of Operation

The ADS8341 is a classic successive approximation register (SAR) A/D converter. The architecture is based on capacitive redistribution, which essentially includes a sample and hold function. The converters are fabricated in 0.6 μm CMOS process. The basic operation of the ADS8341 is shown in the figure below. This device requires an external reference and an external reference clock. It operates from a single supply of 2.7V to 5.25V. The external reference can be any voltage between 500mV and +VCC. The value of the reference voltage directly sets the input range of the converter. The average parameter input current depends on the slew rate of the ADS8341. The analog inputs to the converter are differential inputs provided through a four-channel multiplexer. Inputs can be either providing the voltage on the COM pins (of which two of the four are typically used to differentiate or differential input channels (CH0 - CH3). The specific configuration is selectable via the digital interface.

analog input

Figure 2 shows the block diagram of the ADS8341 input multiplexer. The differential input of the converter is derived from one or two of the four inputs referenced to COM. This control bit is available serially through the DIN pin, see the Digital Interface section of this data sheet for more details. When the converter enters holdover mode, the difference between the voltages +IN and -IN inputs, as shown in the figure below, is captured on the internal capacitor array. The voltage on this -IN input is limited between -0.2V and -0.2V

1.25V, allowing the input to reject small signals common to the +IN and -IN inputs. The +IN input has a range of -0.2V to +VCC +0.2V.

reference input

The external reference sets the analog input range. The ADS8341 operates from 500mV to +VCC. Remember that the analog input is

For the difference between the +IN input and the -IN input, see the diagram above. For example, in single-ended mode, with a 1.25V reference and the COM pin grounded, selecting the input channel (CH0-CH3) will correctly digitize the signal range to 0V to 1.25V. If the COM pin is connected to 0.5V, the input range of the selected channel is 0.5V to 1.75V. Regarding the reference, there are several key item inputs and their wide voltage range. As the reference voltage is reduced, the analog voltage weighting code for each digital output is also reduced. This is often called the LSB

(least significant bit) size and equal to the reference voltage divided by 65,536. Any offset or gain error inherent in the LSB side of the A/D converter seems to increase in size, as the reference voltage decreases. For example, if a given converter has an offset of 2LSB with a 2.5V reference, it will typically be 10LSB with a 0.5V reference. In each case, the actual offset of the device is the same, 76µV. Likewise, the noise or uncertainty of the digitized output will increase as the LSB size decreases. The reference voltage is 500mV and the LSB size is 7.6µV. This level is lower than the internal noise of the device. As a result, the digital output code will be unstable and vary by the number of LSBs around the mean value of a. The distribution of output codes will be Gaussian noise and noise can be reduced by simple averaging or applying a digital filter to the continuous conversion result. When using lower reference voltages, care should be taken to provide a clean layout, including adequate bypassing, clean (low noise, low ripple) power supplies, low noise references, and low noise input signals. Because of the smaller LSB size, the converter will also be more sensitive to nearby numbers

signal and electromagnetic interference. The voltage going into the VREF input is not directly buffered to drive the capacitive digital-to-analog converter (CDAC)

part of the ADS8341. Typically, the input current is 13µA with a 2.5V reference voltage. This value will vary in microamps depending on the conversion result. This reference current reduces the rate and reference voltage directly with the two conversions. As the current reference is plotted on each bit decision, clocking the converter more quickly in a given conversion period does not reduce the overall current consumption of the reference current.

digital interface

The figure below shows a typical operational digital interface for the ADS8341. This diagram assumes that the source's digital signal is a microcontroller or digital signal processor with a basic serial interface (note that the digital input is overvoltage tolerant up to 5.5V regardless of +VCC). Every

Communication between the processor and the converter consists of eight clock cycles. A complete conversion can be accomplished with three serial communications for a total of 24 clock cycles on the DCLK input. The first eight cycles are used to provide the control byte through the DIN pin. When the converter has enough information about the following conversion to set up the input multiplexer clock cycles, the control byte completes and the converter enters conversion mode. At this point, the input sample-and-hold enters hold mode. The next 16 clock cycles complete the actual analog-to-digital conversion. Control Byte The following figure also shows the control bits within the position and order control byte. Details about these bits are given in Tables III and IV. The first bit, the 'S' bit, must always be HIGH and indicate the start of the control byte. The ADS8341 will ignore input pins on DIN until a start bit is detected.

clock mode

The ADS8341 can perform successive approximation conversions to an external serial clock or an internal clock. In both clock modes, the external clock shifts data in and out of the device. Selects internal clock mode when PD1 is high and PD0 is low. If the user decides to switch from one clock mode to another, an additional conversion cycle is required before the ADS8341 can switch to the new mode. The extra cycles are required because the PD0 and PD1 control bits need to be written to the ADS8341 before changing the clock mode. When powering the ADS8341 for the first time, the user must use the desired clock mode for the setup. PD0 = 0 for internal clock mode and PD0 = 1 and PD0 = 1 for external clock mode by programming PD1. The ADS8341 should not be set up until the desired clock mode is enabled

Power-down between conversions (ie, PD1 = PD0 = 0). The ADS8341 enters power-saving mode by maintaining the previous clock mode.

external clock mode

In external clock mode, the external clock not only shifts the data in and out of the ADS8341, it also controls the A/D. conversion steps. BUSY will go high for one clock cycle after the last bit of the control byte is clocked in. A successive approximation bit decision is made and appears on DOUT on each of the next 16 falling edges of DCLK (see above). The figure below shows the BUSY timing in external clock mode. Since one clock cycle of the serial clock is consumed to get busy (when the MSB makes the decision), 16 additional clocks must be given to output all 16-bit data; therefore, a conversion requires at least 25 clock cycles to fully Read data. Since most microprocessors communicate in 8-bit transfers, this means additional

A transfer is necessary to capture the LSB. There are two ways to handle this requirement. One is as shown above, where the beginning byte of the next control appears on the ADS8341 at the same time as the LSB is output. This method allows maximum throughput and 24 clock cycles per conversion.

Another method, shown in Figure 2 below, uses 32 clock cycles per conversion; zeros are shifted out on the DOUT line for the last seven clock cycles. BUSY and DOUT go into a high-impedance state when CS goes high; after the next falling edge of CS, BUSY will go low.

Internal clock mode

In internal clock mode, the ADS8341 generates its own internal conversion clock. This relieves the microprocessor from having to generate the SAR conversion clock and allows the conversion results to be read back conveniently at the processor for any clock frequency from 0MHz to 2.0MHz. BUSY goes low at the start of a conversion and returns to high after the conversion is complete. During conversion, BUSY will remain low for up to 8µs. Also, DCLK should be held low during transitions for best noise performance. Conversion result is stored

In the internal register; data may be flushed out of the register at any time after the conversion is complete. If CS is low when BUSY goes low after the conversion, the next falling edge of the external serial clock will go low to write out the MSB on the DOUT line. The remaining bits (D14-D0) will be output following the MSB on each successive clock cycle. CS is high when BUSY goes low

The DOUT line will then remain tri-stated until CS goes LOW, as shown in the figure below. CS does not need to remain LOW after a conversion begins. Note that BUSY is not tri-stated when CS goes high in internal clock mode. Data can be clocked in and out of the ADS8341 in excess of 2.4MHz, provided the minimum acquisition time, tACQ, remains above 1.7µs.