1. General Description The W78ERD2 is an 8-bit microcontroller that is pin and instruction set compatible with the standard 80C52 . w78erd2 contains a 64-kb flash-eprom whose contents can be updated in the system via a loader stored in a secondary 4-kb flash-eprom. Once the content is confirmed, it can be secured. The W78ERD2 also contains 256 bytes of on-chip RAM; 1 KB of auxiliary RAM; four 8-bit, bidirectional, and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timers/counters; and a serial port. These peripherals are all supported by 9 interrupt sources with 4 priority levels. The W78ERD2 has two power reduction modes: idle mode and power down mode, both of which are software selectable. Idle mode shuts down the processor clock but allows peripherals to continue working, while power down mode stops the crystal oscillator for minimal power consumption. Power-down mode can be activated at any time and in any state without affecting the processor.

Functional Description The w78erd2 architecture consists of a core processor that supports 111 different opcodes and references 64kb of program space and 64kb of data space. It is surrounded by various registers; four general purpose I/O ports; one dedicated, programmable 4-bit I/O port; 256 bytes of RAM; 1 kb of auxiliary RAM (auxiliary RAM); three timers/counters; one serial port; and an internal 74373 latch and 74244 buffer, switchable to port 2. This section covers RAM, timers/counters, clocks, power management, reducing EMI emissions, and resets.

Timer/Counter The W78ERD2 has three timers/counters called Timer 0, Timer 1, and Timer 2. Each timer/counter consists of two 8-bit data registers: TL0 and TH0 for timer 0, TL1 and TH1 for timer 1, and TL2 and TH2 for timer 2. The operation of Timer 0 and Timer 1 is similar to that of the W78C52, and these timers are controlled by the TCON and TMOD registers.
W78ERD2/W78ERD2A Timer 2 is controlled by the t2con register. Like timers 0 and 1, timer 2 can operate as an external event counter or as an internal timer, depending on the setting of bit c/t2 in t2 c on. Timer 2 has three modes of operation: capture, auto-reload and baud rate generator. In capture or auto-reload mode, RCAP2H and RCAP2L are reload/capture registers with the same clock speed as timers 0 and 1.
Five 2. Features • 8-bit CMOS microcontroller • Pin compatible with standard 80C52 • Instruction set compatible with 80C52 • Four 8-bit I/O ports; port 0 has internal pull-up resistors enabled by software. • One additional 4-bit I/O port with interrupt and chip select functions • Three 16-bit timers • Programmable clock output • Programmable counter array (PCA) with PWM, capture, compare and watchdog Features • 9 interrupt sources with 4 priorities • Full duplex serial port with framing - error detection and automatic address recognition • 64-kb, system programmable, flash-eprom (ap flash-eprom) • 4- kb auxiliary flash-eprom for loading programs (ld flash-eprom) • 256 bytes of on-chip RAM • 1-kb auxiliary RAM, software selectable • software reset • 12 clocks per machine cycle per machine operation (default). Speeds up to 40 MHz. • The writer sets each machine to cycle through 6 clocks. Speeds up to 20 MHz. • 2 DPTR registers • Low EMI (ALE suppression) • Built-in power management with idle mode and power down mode • Code protection • Software package: - Lead-free (RoHS) DIP 40: W78ERD2A40DL - Lead-free (RoHS) PLCC 44: W78ERD2A40PL - Lead Free (RoHS) PQFP 44: W78ERD2A40FL

Clock W78ERD2 is designed for use with crystal oscillator or external clock. The W78ERD2 integrates a built-in crystal oscillator. In order for the oscillator to work, a crystal must be connected between pins XTAL1 and XTAL2, and a load capacitor can be connected from each pin to ground. Also, if the crystal frequency is higher than 24 MHz, a resistor should be connected between XTAL1 and XTAL2 to provide a DC bias. An external clock is connected to pin XTAL1, while pin XTAL2 should be left disconnected. As required by the crystal oscillator, the XTAL1 input is a CMOS type input. Therefore, the logic 1 voltage should be higher than 3.5 V.
Power Management The W78ERD2 provides two modes: idle mode and power-down mode to reduce power consumption. Both modes are entered by software. The W78ERD2 enters idle mode when the IDL bit in the PCON register is set. In idle mode, the internal clocks of the processor are stopped, while the internal clocks of peripherals and interrupt logic continue to run. When an interrupt or reset occurs, the W78ERD2 will exit idle mode. When the PD bit in the PCON register is set, the W78ERD2 enters power-down mode. In power-down mode, all clocks are stopped, including the oscillator. The W78ERD2 will exit power-down mode when hardware reset or via external interrupt INT0 or INT1 (if enabled).
To reduce EMI emissions If the crystal frequency is less than 25 MHz, set Bit 7 in the option register to 0 to reduce EMI emissions. For more information, see Option Bits.
Reset The external reset signal is sampled at S5P2. To be effective, it must be held high for at least two machine cycles while the oscillator is running, as the W78ERD2 has a special fault cancellation circuit that ignores faults on the reset line. During reset, the port is initialized to FFH, the stack pointer is initialized to 07H, all other SFRs are initialized to 00H, with two exceptions, SBUF is not changed, and bit 4 in PCON is not cleared.

Port 4 and Base Registers Port 4, address E8H is a 4-bit, multipurpose, programmable I/O port. Each bit is individually configurable, and registers p4cona and p4conb contain control bits that select the mode of each pin. Each pin has four operating modes. Mode 0: Bidirectional I/O port, such as port 1. If enabled, P4.2 and P4.3 will act as external interrupts for INT3 and INT2. Mode 1: Read the strobe signal synchronized with the RD signal at the specified address. These signals can be used as chip select signals for external peripherals. Mode 2: Write a strobe signal synchronized with the WR signal at the specified address. These signals can be used as chip select signals for external peripherals. Mode 3: The read/write strobe signal is synchronized with the rd or wr signal of the specified address. These signals can be used as chip select signals for external peripherals. In modes 1–3, the address range of the chip select signals depends on the contents of registers p4xah and p4xal, which contain the high- and low-order bytes of p4.x's 16-bit address comparator, respectively. The following diagram illustrates this.

For example, the following program sets P4.0 as the write strobe for I/O port addresses 12 34H −1237H with positive polarity, while P4.1 − P4.3 are used as regular I/O ports.

MOV P40AH, 35; 12H MOV P40AL, 35; 34H; the basic I/O address of P4.0 is 1234H. MOV P4CONA, 35; 001010B; P4.0 is the write strobe; addresses A0 and A1 are masked. mov p4conb, 35; 00h; p4.1 p4.3 are regular I/O ports mov p2econ, 35; 10h sets p40sinv to 1 and inverts the p4.0 write strobe to positive. Then, any instruction movx@dptr,a (where dptr is at 1234h) generates positive polarity, write strobe on pin p4.0, while instruction mov p4,x35;xx places 3 bits on p4.3 pin 4.1

Interrupts This section provides more information on the external interrupts int2 and int3 and provides an overview of interrupt priorities and polling sequences.
External Interrupts 2 and 3 The W78ERD2 provides two additional external interrupts, INT2 and INT3, similar to the external interrupts INT0 and INT1 in the standard 80C52. These interrupts are configured by the xicon (external interrupt control) register, which is not a standard register in the 80c52. Its address is 0c0h. xicon is bit-addressable; for example, "setb 0c2h" sets the ex2 bit of xicon.
8.2 Interrupt Priority Each interrupt has one of four priority levels in the W78ERD2 as shown below

Programmable Timer/Counter The W78ERD2 has three 16-bit programmable timer/counters. Time Base Selection The W78ERD2 provides two speeds for the timer. The timer counts at 1/12 the clock, the same speed as in the standard 8051 series. Alternatively, the timer can count at 1/6 of the clock, called turbo mode. This speed is controlled by the T0M, T1M and T2M bits in CKCON. The default value is zero, which selects 1/12 of the clock. These 3 bits (T0M, T1M, and T2M) have no effect if option bit 3 is set to 1 to select 12 clocks/machine cycles.
Timer 0 and Timer 1 Timer 0 and 1 each have a 16-bit timer/counter consisting of two 8-bit registers: Timer 0 consists of th0 (8 msb) and tl0 (8 lsb), Timer 1 consists of th0 (8 msb) and tl0 (8 lsb) Consists of th1 and tl1. These timers/counters can be configured to operate as timers, machine cycle counters, or counters based on external inputs. The "timer" or "counter" function itself is selected by the corresponding "tc/" bits in the TMOD register: bit 2 of timer 0 and bit 6 of timer 1. Additionally, each timer/counter can operate in one of four possible modes selected by bits m0 and m1 in TMOD. The rest of this section explains the timer's time base, then describes each mode. Mode 0 In Mode 0, the timer/counter is a 13-bit counter, where the 8 MSBs are in THX and the 5 LSBs are the 5 lower bits in TLX. The upper three digits in TLX are ignored. Because THX and TLX are read separately, the timer/counter acts like an 8-bit counter with a 5-bit, divide-by-32 prescale. Counting is only enabled when trx is set and gate=0 or intx=1. The count of the timer/counter depends on tc/. When tc/ is set to 0, the timer/counter counts the negative edge of the clock according to the time base selected by bit txm in ckcon. When tc/ is set to 1, it counts falling edges on t0 (p3.4, timer 0) or t1 (p3.5, timer 1). When the 13-bit counter reaches 1ffh, the next count will roll on the timer/counter to 0000h and set the timer overflow flag tfx(in tcon). If enabled, an interrupt will occur.

Mode 1 Mode 1 is similar to Mode 0, except that the timer/counter is a 16-bit counter instead of a 13-bit counter. Use all bits in THX and TLX. The rollover happens when the timer moves from ffffh to 0000h. Mode 2 Mode 2 is similar to Mode 0, except that TLX acts like an 8-bit counter, and THX holds the auto-load value of TLX. When the tlx register overflows from ffh to 00h, the timer overflow flag tfx bit (in tcon) is set, tlx is reloaded with the contents of thx, and the counting process continues. The reload operation does not affect the THX register.

Mode 3 Mode 3 is used when an additional 8-bit timer is required, and it affects Timer 0 and Timer 1 differently. Timer 0 splits tl0 and th0 into two separate 8-bit count registers. TL0 uses timer 0 control bits tc/, gate, tr0, int0 and tf0 to count clock cycles (clock/12 or clock/6) or falling edge of pin t0. At the same time, TH0 receives TR1 and TF1 from timer 1 and can count clock cycles (clock/12 or clock/6). Mode 3 simply freezes timer 1, which provides a way to turn the timer on and off. When Timer 0 is in Mode 3, Timer 1 can still be used in Modes 0, 1, and 2, but with limited flexibility. Timer 1 can still be used as a timer/counter (or baud rate generator for serial ports) and retains use of gate and int1 pins, but it no longer controls overflow flag tf1 and enable bit tr1.

Timer/Counter 2 Timer 2 is a 16-bit up/down counter with capture/reload function. It is configured by the t2mod register and controlled by the t2con register. Like timers 0 and 1, timer 2 can count clock cycles (fosc/12 or fosc/6) or an external T2 pin (selected by t2c/) and has four modes of operation, each of which is discussed below. Capture Mode Capture mode is enabled by setting the rl2 cp/bit in the t2con register. In capture mode, Timer 2 acts as a 16-bit up-counter. When the counter rolls from ffffh to 0000h, a tf2 bit is set, and if enabled, an interrupt is generated. If the exen2 bit is set, then a negative transition on the t2ex pin will capture the value in the tl2 and th2 registers in the rcap2l and rcap2h registers. This operation also causes the exf2 bit in t2con to be set, which may also generate an interrupt.

Auto-reload mode, enabled by clearing the rl2 cp/bit in t2con and the dcen bit in t2mod to enable the mode count. In this mode, Timer 2 is a 16-bit up-counter. When the counter rolls from ffffh to 0000h, the contents of rcap2l and rcap2h are automatically reloaded into tl2 and th2, and the timer overflow bit d2 is set. A negative transition of the t2ex pin also causes a reload if the exen2 bit is set, which also sets the exf2 bit in t2con.

Auto reload mode, count up/down This mode is enabled when the rl2 cp/bit in t2con is cleared and the dcen bit in t2mod is set. In this mode, Timer 2 is an up/down counter whose direction is controlled by the t2ex pin (1=up, 0=down). When timer 2 overflows while counting up, the counter is reloaded by rcap2l and rcap2h. When timer 2 is counting down, when timer 2 is equal to rcap2l and rcap2h, the counter is reloaded with ffff. In either case, the timer overflow bit d2 is set, and the exf2 bit is toggled, although exf2 cannot generate interrupts in this mode.

Baud Rate Generator Mode The baud rate generator mode is enabled by setting the rclk or tclk bits in the t2con register. In baud rate generator mode, timer 2 is a 16-bit up-counter that is automatically reloaded on overflow, but this overflow does not set the timer overflow bit. If exen2 is set, a negative transition on the t2ex pin will set the exf2 bit in t2con and, if enabled, generate an interrupt request.

Mode 0 Mode 0 is a half-duplex, synchronous mode. RxD transmits and receives serial data, and TXD transmits the shift clock. The TXD clock is provided by the W78ERD2. 8 bits are sent or received per frame, LSB first. The baud rate is fixed at 1/12 of the oscillator frequency. The functional block diagram is shown below.

As before, data goes in and out of the serial port on the RxD. The TXD line provides the shift clock, which shifts data in and out of the W78ERD2 and the device on the other end of the line. Any command written to sbuf will initiate a transfer. The shift clock is activated and data is shifted out on the RxD pin until all 8 bits have been transferred. If sm2 is set to 1, data will appear on rxd one clock cycle before the falling edge of txd, then the txd clock will remain low for two clock cycles before going high again. If sm2 is set to 0, the data is displayed on rxd three clock cycles before the falling edge of txd, and the txd clock then remains low for 6 clock cycles before going high again. This ensures that the receiving device can clock the RXD data on the rising edge of TXD or when the TXD clock is low. Finally, once the last bit has been transmitted, the ti flag is set high in c1. When REN is 1 and RI is zero, the serial port receives data. The TXD clock is active and the serial port latches on to data on the rising edge of the shift clock. Therefore, the external device should display data on the falling edge of TXD. This process continues until all eight bits are received. Then, after the last rising edge on TXD, the RI flag is set high in C1, stopping reception until software clears RI.
Mode 1 Mode 1 is a full-duplex asynchronous mode. A serial communication frame consists of 10 bits transmitted on TXD and received on RXD. The 10 bits consist of a start bit (0), 8 data bits (LSB first), and a stop bit (1). When w78erd2 receives data, the stop bit goes to rb8 in scon. The baud rate is 1/16 or 1/32 of the Timer 1 overflow and can be set to various reload values. (The 1/16 or 1/32 coefficient is determined by the SMOD bit in the PCON SFR.) The functional diagram is shown below.
Spuff

The transfer begins when data is written to the SBUF, but in synchronization with the rollover of Timer 1 (divided by 16 or 32 as configured), not the write signal. w78erd2 waits for the next roll of timer 1 (divide by 16 or 32) before putting the data into the txd. The next bit is placed on the txd after the next flip. After all 8 bits of data have been transferred, the stop bit is transferred. Finally, the ti flag is set at the tenth toggle after the write signal. Reception is enabled only when REN is high. The W78ERD2 samples the RxD line at 16 times the selected baud rate, looking for falling edges. When a falling edge is detected on the RxD pin, Timer 1 (divided by 16 or 32) is immediately reset to better align the bit boundaries and the serial port starts receiving data. The 16 states of the counter effectively divide the time into 16 slices, and the bit detection is done using the 8th, 9th, and 10th states in the three best states. If the start bit is invalid (1), reception is aborted and the serial port continues to look for a falling edge on RxD. If the start bit is valid, eight data bits are shifted in. Then, if (1) ri = 0 and (2) sm2 = 0 or stop bit = 1, the stop bit is put into rb8, the data is put into sbuf, and ri is set. Otherwise, received frames may be lost. In the middle of the stop bit, w78erd2 continues to look for a falling edge on RxD.
Mode 2 Mode 2 is a full-duplex asynchronous mode. A serial communication frame consists of 11 bits, transmitted on TXD and received on RXD. The 11 bits consist of a start bit (0), 8 data bits (LSB first), a programmable 9th bit (TB8), and a stop bit (1). The 9th bit is read into and transferred from RB8. The baud rate is 1/32 or 1/64 of the oscillator frequency, and the 1/32 or 1/64 factor is determined by the SMOD bit in the PCON SFR. The function diagram is shown below.

When data is written to the SBUF, the transfer begins, but is synchronized with the rollover of the counter (divided by 32 or 64 as configured), not with the write signal. w78erd2 waits for the next roll of the counter (divide by 32 or 64), then puts the data into the txd. The next bit is placed on the txd after the next flip. After all 9 bits of data are transmitted, the stop bit is transmitted. Finally, the ti flag is set at the eleventh toggle after the write signal. Reception is enabled only when REN is high. The W78ERD2 samples the RxD line at 16 times the selected baud rate, looking for falling edges. When a falling edge is detected on the RxD pin, the counter (divided by 32 or 64) is immediately reset to better align the bit boundaries and the serial port starts receiving data. The 16 states of the counter effectively divide the time into 16 slices, and the bit detection is done using the 8th, 9th, and 10th states in the three best states. If the start bit is invalid (1), reception is aborted and the serial port continues to look for a falling edge on RxD. If the start bit is valid, the remaining bits will be shifted in. Then if (1) ri = 0 and (2) sm2 = 0 or received 9th bit = 1, put the 9th bit in rb8, put the data in sbuf, and set ri. Otherwise, received frames may be lost. In the middle of the stop bit, w78erd2 continues to look for a falling edge on RxD.
Mode 3 Mode 3 is similar to Mode 2 in all respects, except that the baud rate can be programmed in the same way as in Mode 1. The function diagram is shown below.

10.5 Framing Error Detection A framing error occurs when a valid stop bit is not detected. This may indicate incorrect serial data communication. Typically, framing errors are caused by noise or contention on serial communication lines. The W78ERD2 is able to detect framing errors and set a flag that can be checked by software. Framing error fe bit is in scon.7. In the standard 8051 family, this bit is usually used as SM0. However, in w78erd2 it has a dual function called sm0/fe. There are actually two separate markers, one for SM0 and one for FE. The flag actually accessed as scon.7 is determined by the smod0 (pcon.6) bit. When smod0 is set to 1, the fe flag is accessed. When smod0 is set to 0, the sm0 flag is accessed. The FE bit is set to 1 by hardware but must be cleared by software. Once fe is set, any frames received afterward, even without any errors, do not clear the fe flag. This flag must be cleared by software. Note that SMOD0 must be set to 1 when reading or writing FE.

Multiprocessor Communication Multiprocessor communication uses the 9th data bit in modes 2 and 3. In W78ERD2, the ri flag is only set when the received byte corresponds to a given or broadcast address. This hardware feature eliminates the software overhead required to check each receive address and greatly simplifies the task of the software programmer. In multiprocessor communication mode, the address byte is distinguished from the data byte by the ninth bit, which is set high for the address byte. When the master processor wants to transfer a block of data to one of the slaves, it first sends the address of the target slave (or slaves). All slaves should have their sm2 bits set high when waiting for an address byte. This ensures that they are only interrupted by the receipt of an address byte. The automatic address recognition feature ensures that only addressed slaves are actually interrupted because address comparison is done by hardware and not software. Addressing the slave clears the SM2 bit, thereby clearing the way the data byte is received. When sm2=0, the slave is interrupted on receiving each complete data frame. Unaddressed slaves are not affected because they are still waiting for their address. The master processor can selectively communicate with the slave group using the given address. All slaves can be addressed together using the broadcast address. The address of each slave is defined in the SADDR and SADEN registers. The slave address is an 8-bit value specified in the SADDR SFR. saden sfr is actually a mask of byte values in saddr. If a bit position in saden is 0, the corresponding bit position in saddr is not significant. Only bit positions in saddr for which the corresponding bit in sadden is 1 are used to obtain a given address. This gives the user the flexibility to handle multiple slaves without having to change the slave addresses in SADDR. The example below shows how the user can define a given address to address different slaves.