The C8051F300 /1/2/3/4/5 devices are fully integrated mixed-signal system-on-chip MCUs. The highlighted functions are listed below. For specific product feature selections.

High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)

In-system, full-speed, non-intrusive debug interface (on-chip)

True 8-bit 500 ksps 11-channel ADC with programmable gain preamplifier and analog multiplexer (C8051F300/2 only)

Precision Programmable 25 MHz Internal Oscillator

Up to 8 kB on-chip flash memory

256 bytes of on-chip RAM

SMBus/I2C and enhanced UART serial interface, implemented in hardware

Three general-purpose 16-bit timers

Programmable Counter/Timer Array (PCA) with Three Capture/Compare Modules and Watchdog Timer Function

On-chip power-on reset, VDD monitor and temperature sensor

On-chip voltage comparator

Byte-wide I/O port (5 V tolerant)

With on-chip power-on reset, VDD monitor, watchdog timer and clock oscillator, the C8051F300/1/2/3/4/5 devices can be realized as true stand-alone system-on-chip solutions. Flash memory can be reprogrammed even in-circuit, providing non-volatile data storage and allowing field upgrades of the 8051 firmware. User software has full control of all peripherals and can individually shut down any or all peripherals to save power. The on-chip Silicon Laboratories 2-wire (C2) development interface allows non-intrusive (without using on-chip resources), full-speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspecting and modifying memory and registers, setting breakpoints, single step, run and pause commands. When debugging, all analog and digital peripherals are fully functional using C2. Two C2 interface pins can be shared with user functions, allowing package pins to be freed during system debugging. Each device has an operating temperature range of 2.7 to 3.6 V and an operating temperature range of -45 to +85°C. Port I/O and RST pins can tolerate input signals up to 5 V. The C8051F300/1/2/3/4/5 are available in 3 x 3 mm 11-pin QFN or 14-pin SOIC packages.

C8051F300/2 Block Diagram

C8051F301/3/4/5 Block Diagram

The C8051F300/1/2/3/4/5 family uses Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51 ™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core provides all the peripherals that come with the standard 8052, including two standard 16-bit counter/timers, one enhanced 16-bit counter/timer input with external oscillator, full dual with extended baud rate configuration UART, 256 bytes of internal RAM, 128 bytes of Special Function Register (SFR) address space and byte-wide I/O ports. 1.1.2. Increase throughput

The CIP-51 adopts a pipelined architecture, which greatly improves the instruction throughput compared to the standard 8051 architecture. In the standard 8051 all instructions except MUL and DIV are executed in 12 or 24 system clock cycles with a maximum system clock of 12 to 24 MHz. In contrast, the CIP-51 core executes 70% of the instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles.

Additional features:

The C8051F300/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and peripherals that improve end-application performance and ease of use. The extended interrupt handler provides 12 interrupt sources for the CIP-51 (compared to 7 for the standard 8051), allowing a large number of analog and digital peripheral interrupt controllers. Interrupt-driven systems require less MCU intervention, providing more efficient throughput. Additional Interrupts Source code is very useful when building multitasking real-time systems. Provides 8 reset sources: power-on reset circuit (POR), on-chip VDD monitor (forced reset) when supply voltage is below 2.7 V, watchdog timer, missing clock detector, voltage level detection from Comparator0, Forced software reset, external reset pin and illegal flash read/write protection circuit. Every reset source except POR, reset input pin or flash protection can be disabled in software by the user. The WDT can be permanently enabled in software after a power reset during MCU initialization. The internal oscillator is available as a factory calibrated 24.5 MHz ±2% (C8051F300/1 devices); uncalibrated versions are available for C8051F302/3/4/5 devices. On all C8051F300/1/2/3/4/5 devices, the internal user can program the oscillator period in ~0.5% increments. An external oscillator driver circuit is also included, allowing an external crystal, ceramic resonator, capacitor, RC or CMO clock source to generate the system clock. The system clock source can be switched on-the-fly to an external oscillator circuit if desired. External oscillators are useful in low power applications, allowing the MCU to run from a slow (power saving) external crystal source while periodically switching to the fast (up to 25 MHz) internal oscillator as needed.

On-chip clock and reset

On-chip memory:

The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM with the upper 128 bytes double mapped. Indirect addressing accesses the general upper 128 bytes of destination RAM and direct addressing accesses the 128 bytes SFR address space. The lower 128 bytes of RAM can be accessed by direct and indirect addressing. The first 32 bytes can be addressed as four banks of general purpose registers, the next 16 bytes can be byte-addressable or bit-addressable. The C8051F300/1/2/3 contain 8k bytes of Flash program memory (C8051F304 contains 4k bytes; C8051F305 contains 2k bytes). The memory can be reprogrammed in-system in 512-byte sectors and does not require special off-chip programming voltages.

On-chip debug circuit:

The C8051F300/1/2/3/4/5 devices include on-chip Silicon Labs 2-wire (C2) debug circuitry that provides non-intrusive, full-speed, in-circuit debugging of production parts installed in the final application. Silicon Labs' debug system supports inspection and modification of memory and registers, breakpoints and single stepping. No additional target RAM, program memory, timers or communication channels are required. All digital and analog peripherals are functional and will work when debugging. All peripherals (except ADC and SMBus) stop stepping during MCU stop, single period, or at breakpoints, to stay in sync.

The C8051F300DK Development Kit provides all the hardware and software required to develop application code and in-circuit debugging with C8051F300/1/2/3/4/5 MCUs. The kit includes software using the developer's studio and debugger, an integrated 8051 assembler and a C2 debug adapter. It also has a target application board with the associated MCU and large prototyping area installed, as well as the necessary communication cables and wall-mounted power supplies. The development kit requires a computer with Windows® 98SE or later. Compared to standard MCU emulators that use an onboard "ICE chip" and require an onboard "ICE chip", the Silicon Labs IDE interface has an extremely high development and debug configuration. The MCU in the application board needs to be plugged in. Silicon Labs' debug paradigm increases ease of use and maintains the performance of precision analog peripherals.

Perhaps the most unique port I/O enhancement is the digital crossbar. This is essentially a digital switching network that allows internal digital system resources to be mapped to port I/O pins (see diagram below). On-chip counters/timers, serial buses, HW interrupts, comparator outputs and other digital signals in the controller can be configured to appear on the port I/O pins specified in the crossbar control register. This allows the user to select the exact combination of general purpose port I/O and specific digital resources required for the application.

Programmable Counter Array

In addition to three 16-bit general purpose counters/timers, an on-chip Programmable Counter/Timer Array (PCA) is included. The PCA consists of a dedicated 16-bit counter/timer time base and three programmable capture/compare modules. The PCA clock is derived from one of six sources: system clock divided by 12, system clock divided by 4, timer 0 overflow, external clock input (ECI), system clock, or external oscillator clock source divided by 8. External clock source It is useful to select the real-time clock function, where the PCA is clocked by an external source from the internal oscillator to drive the system clock. Each capture/compare module can be configured to operate in one of six modes: edge-triggered capture, software timer, high-speed output, 8- or 16-bit pulse width modulator, or frequency output. Additionally, Capture/Compare Module 2 provides a Watchdog Timer (WDT) function. After a system reset, module 2 is configured and enabled in WDT mode. PCA capture/compare module I/Os and external clock inputs can be routed to port I/Os through digital crossbar switches.

8-bit ADC (C8051F300/2 only)

The C8051F300/2 includes an on-chip 8-bit SAR ADC with a 10-channel differential input multiplexer and programmable gain amplifier ADC with a maximum throughput of 500 ksps and a true 8-bit precision INL of ±1LSB. The ADC system includes a configurable analog multiplexer that selects positive and negative ADC inputs. Each port pin can be used as ADC input; in addition, the on-chip temperature sensor output and supply voltage (VDD) can be used as ADC input. User firmware may turn off the ADC to save power. An integrated Programmable Gain Amplifier (PGA) amplifies the ADC input by 0.5, 1, 2, or 4, as defined by user software below. The gain stage is especially useful when the input voltage signal varies greatly between different ADC input channels, or when it is necessary to "amplify" a signal with a large DC offset. Conversion can be started in five ways: software command, overflow of timer 0, 1 or 2, external conversion start signal. This flexibility allows the start of a conversion to be triggered by a software event, a periodic signal (timer overflow) or an external HW signal. Conversion completion is indicated by a status bit and an interrupt (if enabled). After completing a, the resulting 8-bit data word is latched into the SFR for conversion.

The Window Compare register for ADC data can be configured to interrupt the controller when ADC data is within or outside the specified range. The ADC can continuously monitor critical voltages in background mode without interrupting the controller unless the converted data is within/outside of the specified range.

8-bit ADC block diagram

Compare

The C8051F300/1/2/3/4/5 devices include an on-chip voltage comparator that can be enabled/disabled and configured by user software. All port I/O pins can be configured as comparator inputs. If desired, two comparator outputs can be routed to port pins: a latched output and/or an unlatched (asynchronous) output. The comparator response time is programmable, allowing the user to choose between high-speed and low-power modes. Positive and negative hysteresis is also configurable. Comparator interrupts can be generated on rising, falling, or both edges. In idle mode, these interrupts can be used as "wake-up" sources. The comparator can also be configured as a reset source.