The AD420 is a complete digital to current loop output converter designed to meet the needs of the industrial control market. It provides a high precision, fully integrated, low cost single chip solution for generating current loop signals in a compact 24-pin SOIC or PDIP package. The output current range is programmable from 4 mA to 20 mA, 0 mA to 20 mA, or 0 mA to 24 mA for the overrange function. The AD420 can also provide a voltage output from a separate pin that can be configured to provide 0 V to 5 V, 0 V to 10 V, ±5 V or ±10 V, with the addition of an external resistive buffer amplifier. The 3.3 Mbaud serial input logic design minimizes cost with galvanic isolation and can often be easily interfaced to used microprocessors. It can be used in 3-wire or asynchronous mode and the serial output pin is used to allow daisy-chaining of multiple DACs on the current loop side of the isolation barrier.

The AD420 uses sigma-delta (Σ-Δ) DAC technology to achieve 16-bit monotonicity at a very low cost. Full settlement to 0.1% occurs within 3 ms. The only external components required (besides the normal transient protection circuitry) are two low-cost capacitors with a DAC output filter. If the AD420 is used with extreme temperatures and power supply voltages, external output transistors can be used to minimize power dissipation on the chip through the BOOST pin. Error The DETECT pin is signaled when an open circuit occurs in the loop. An on-chip voltage reference can be used to provide accuracy. In addition to the AD420, +5V can be applied to external components. Users want temperature stability in excess of 25 ppm/°C. An external precision voltage reference such as the AD586 can be used as a reference. AD420 is available in 24-pin SOIC and

The PDIP operating temperature range is -40°C to +85°C.

Functional block diagram

feature

4 mA-20 mA, 0 mA-20 mA or 0 mA-24 mA

Current output

16-bit resolution and monotonicity

±0.012% maximum integral nonlinearity

±0.05% maximum offset (trimmable)

±0.15% maximum total output error (can be fine-tuned)

Flexible Serial Digital Interface (3.3 MBPS)

On-chip loop fault detection

On-chip 5 V reference (25 ppm/°C max)

Asynchronous CLEAR function

The maximum supply range is 32 V.

Output Loop Compliant 0 V to VCC - 2.75 V

24-pin SOIC and PDIP packages

1. The AD420 is a single chip solution that generates a 20 mA or 0 mA to 20 mA signal current loop at the 4 mA current controller side.

2. AD420 power supply range is 12 V to 32 V. Output loop compatibility is 0 V to VCC - 2.75 V.

3. Flexible serial input can be used in 3-wire mode using SPI 174 ; or MICROWIRE® microcontrollers, or using asynchronous mode, minimizing the number of control signals needed.

4. The serial data output pins can be used to daisy-chain any number of AD420s together in 3-wire mode.

5. On power-up, the AD420 initializes its output to a low level at the end of the selected range.

6. The AD420 has an asynchronous CLEAR pin that can send the output to the low end of the selected range (0 mA, 4 mA, or 0 V).

7. AD420 BOOST pin can accommodate external pin transistor can reduce the power consumption of the chip.

8. The offset is ±0.05%, and the total output error is ±0.15% If required, it can be trimmed using two external potentiometers.

Pin Configuration and Functional Description

Pin function description

VLL auxiliary buffer +4.5 V digital logic voltage. This pin is the digital internal supply voltage circuit and can be used as a termination for pull-up resistors. An external +5 V power supply can be connected to the VLL. It will override this buffer voltage, reducing internal power dissipation. The VLL pin should be decoupled to GND with a 0.1µF capacitor. See the Power and Decoupling section.

Fault Detection Fault Detection is connected to a pull-up resistor and is set low to the programmed value of the DAC when the output current does not match, for example, in the event of an open current loop.

RANGE SELECT 2 selects the output operating range of the converter. one output voltage range and three

RANGE SELECT 1 output current range available.

CLEAR valid VIH unconditionally forces the output to the minimum value of its programmed range. Removing the DAC output after CLEAR will maintain this value. The data in the input registers is not affected.

LATCH loads serial input register data into the DAC in parallel with rising edges in 3-wire interface mode. To use asynchronous mode connect LATCH to VCC through a current limiting resistor.

Clock Data Clock Input. The clock period is equal to 1x the bit rate of the input data bits in 3-wire interface mode in asynchronous mode.

Serial data input data.

DATA OUT serial data output. In 3-wire interface mode, this output can be used to daisy-chain multiplex AD420s. In asynchronous mode, a positive pulse will indicate frame error reception after the stop bit.

GND ground (common).

REF OUT +5 V Reference Output.

REF IN Reference input.

OFFSET TRIM offset adjustment.

VOUT voltage output.

IOUT current output.

BOOST is connected to an external transistor to reduce power dissipation in the AD420 output transistor, if desired.

CAP 1 These pins are used for internal filtering. Connect capacitors between each

CAP 2 pin and VCC. See the description of the current output action.

NC is not connected. Do not connect anything to this pin.

VCC power input. The VCC pin should always be decoupled to GND with a 0.1µF capacitor. See Power and Decoupling section.

Three-Wire Interface Fast Edge on Digital Lines

INPUT

One of the serial inputs has a fast rising edge (<100 ns)

(CLOCK, DATA IN, LATCH) while the other input is logic high,

This part may be triggered into test mode and content

data registers may be corrupted, which may cause

The value loaded by the output is incorrect. if it's a fast edge

Expected on the digital input line, it is recommended to use

During serial loading of the DAC, the latch line remains at logic 0.

Also during the update the clock line should be kept low

DAC via the latch pin. Alternatively, add a small

Capacitance values on the digital lines will slow down the edges.

Asynchronous interface

Note that in the timing diagram for asynchronous mode operation, each data word consists of a START (0) bit followed by a STOP frame (1) bit. Data timing is relative to the rising edge of CLOCK at the center of each bit cell. The bit unit is a 16 clock long, and the first unit (START bit) follows the leading edge (falling edge) of the START bit from the first clock. So MSB ( D15 ) samples the START bit 24 clock cycles after the start, D14 samples at clock number 40, and so on. The IN pin must be held at logic 1 for any dead time before writing the next word DATA. When a STOP bit is received, the DAC output is updated. In the case of a frame error (the STOP bit is sampled as 0) the AD420 will output a cycle-wide STOP bit within the clock cycle after the DATA OUT pin is sampled with a clock pulse. If framing, the DAC output will not update if an error is detected.

Resolution

For 16-bit resolution, 1 LSB = 0.0015% of the FSR. In the 4 mA-20 mA range 1 LSB = 244 nA. Integral Nonlinearity Analog Devices defines integral nonlinearity as the maximum actual adjusted DAC output deviation from the ideal analog output (straight line from 0 to FS - 1 LSB) for any combination of bits. This is also called relative accuracy.

Differential nonlinearity

Differential nonlinearity is a measure of change in the analog output, normalized to full scale, in relation to the LSB of the changing digital input code. Monotonic behavior requires a differential linearity error greater than -1 LSB over the temperature range of interest.

Monotonicity

If the output increases or stays, the DAC is a monotonic constant increasing digital input, the result is that the output will always be a single-valued function of the input.

gain error

Gain Error is a measure of the output error between the ideal DAC and the actual device output, after the offset is loaded with all-ones errors that have been adjusted out.

offset error

Offset error is the deviation of the output current from the ideal value expressed as a percentage of full-scale output with 0 loaded in the DAC.

drift

Drift is the change in parameters such as gain and offset over a specified temperature range. Drift temperature coefficient, expressed in ppm/°C, is calculated by measuring the parameters at TMIN, 25°C and TMAX and dividing by the change in the parameter by the corresponding temperature change.

Current Loop Voltage Compliance

Voltage compatibility is that the maximum voltage output current at the IOUT pin will be equal to the programmed value.

Theory of Operation

The AD420 uses a sigma-delta (Σ-Δ) architecture for digital-to-analog conversion. This architecture is especially well suited for relatively low bandwidth demanding industrial control environments due to its inherent high-resolution monotonicity.

In the AD420, a second-order modulator is used to minimize complexity and chip size. A single-bit stream modulator from a switched current source is partially filtered by two continuous-time resistor-capacitors. Capacitors are the only external components necessary to add standard current output operation. The filtered current is amplified and mirrored to the supply rails so that the application only needs to see the 4 mA-20 mA, 0 mA-20 mA, or 0 mA-24 mA current source output relative to ground. The AD420 is fabricated in a BiCMOS process and is ideal for implementing high-performance low-voltage digital logic and high-voltage analog circuits.

The AD420 can also provide a voltage output instead of a current loop output if desired. The addition of an external amplifier allows to obtain 0 V-5 V, 0 V-10 V, ±5 V or ±10 V. The D420 has a loop fault detection circuit that can warn

The voltage at IOUT attempts to exceed the compliance range of the open loop circuit or the supply voltage is insufficient. The fault detection is a valid low open-drain signal, so one can connect several AD420s to a single pull-up resistor for global error detection. Pull-up resistors can be connected to the VLL pin or to an external +5 V logic supply. The IOUT current is controlled by a PMOS transistor with an internal amplifier as shown in the functional block diagram.

The internal circuitry that generates the fault output avoids the use of a comparator with a window limit, as this requires the actual output to be falsely active before the FAULT DETECT output. Conversely, the internal amplifier of the AD420 output stage is less than about 1 volt of drive capability remaining when the signal is generated (when the gate of the output PMOS transistor almost reaches ground. Therefore, the FAULT DETECT output activates slightly before reaching the compliance limit. Due to conducting For comparison, within the feedback loop of the output amplifier, the output maintains accuracy through open-loop gain, and no output error occurs until the fault detection output becomes active.

3-wire digital interfaces, including DATA IN, CLOCK, and LATCH, connect all commonly used serial microprocessors without adding any external glue logic. The data is loaded into the input register under the control of CLOCK and loaded into the DAC when LATCH is enabled. If the user wants to substantially reduce the number of galvanic isolators for safety applications, the AD420 can be configured to operate in asynchronous mode. Select this mode by connecting the LATCH pin to VCC through a current limiting resistor. The data must then be combined with start and stop bits to construct the framing information and trigger the internal LATCH signal.