HIP6018B is a high-efficiency synchronous single-phase PWM controller with single-loop control design, with voltage monitoring function, overvoltage and overcurrent protection function, and voltage monitoring function. It can provide accurate core voltage supply for high-performance processors, and can also provide 1.5V and 2.5V power supply voltages for computers. HIP6018 power IC chip includes 1 PWM controller, 1 linear comparator and 1 linear controller , and also includes a 5-bit digital-to-analog converter to read the voltage identification signal (VID signal) directly from the processor.

The input voltage of HIP6018 power IC chip is 3.5V, 5V and 12V, the output main voltage is 1.8~3.5V, and it can also output 1.5V and 2.5V auxiliary voltage. The output main voltage is controlled by the 2~6 pins of HIP6017, Controlling the level combination of these pins can increase or decrease the output voltage with 0.05V accuracy between 1.80~2.05V; and increase or decrease it with 0.1V accuracy between 2.1~3.5V. HIP6018B adopts 24-pin SOIC package.

initialization

The HIP6018B automatically initializes the force upon receipt of the input. No special sequence of input power is necessary. A power-on reset (POR) function continuously monitors the input supply voltage. The power-on reset monitors the bias voltage (+12VIN) on the VCC pin, the 5V input voltage (+5VIN) on the OCSET1 pin, and the VIN2 3.3V input pin. The normal level on OCSET1 is equal to +5VIN less a fixed voltage drop on the network connection. Power-on reset after all three input power start functions, soft start operation voltage exceeds its POR threshold.

figure 1

soft start

A power-on reset function initiates a soft-start sequence. Initially, the voltage on the SS pin rises rapidly to about 1V (this minimizes the soft-start interval). Then the external capacitor (CSS) charged by the internal 11µA current source on the SS pin is 4V. The reference input (+ terminal) and output (COMP1 pin) of the PWM error amplifier are clamped to a level proportional to the SS pin voltage. When the SS pin voltage slews from 1V to 4V, the output clamp generates a pulse capacitor(s) in phase that charge the output with increasing width. After this initial phase, the reference input clamp slows down the output voltage rate by multiple layers and provides a smooth transition to the Hinal set voltage. Also the reference voltage input of the linear regulator clamps the voltage proportional to the SS pin voltage. This method provides a fast and controlled rise of the output voltage. Figure 1 shows a typical soft-start sequence application. The SS voltage at T0 rises rapidly to about 1V. At T1, the SS pin and the error amplifier output voltage reach the triangular valley of the oscillator. The oscillator's triangle wave is compared to clamp the error amplifier ER output voltage. As the SS pin voltage increases, the pulse width at the phase pin increases. The interval of increasing pulse width continues until each output reaches sufficient voltage to transmit the control and input reference clamps. If we consider the 2.0V output (VOUT1) in Figure 1, this time occurs at T2. During T2 and T3, the spacing between the error amplifier reference ramps to the final value and the converter regulates the output voltage proportional to the SS pin voltage. At time t3, the input clamp voltage exceeds the reference voltage and the output voltage is in regulation.

The remaining outputs are also programmed to follow the SS pin voltage. Each linear output (VOUT2 and VOUT3) initially follows a ramp similar to the PWM output. The input reference clamp slows the rate of rise of the output voltage when each output reaches sufficient voltage. The PGOOD signal toggles "high" when all output voltage levels have exceeded their undervoltage levels. See the Soft Start Next Application Guide Intervals procedure to determine the soft start interval.

figure 2

Failsafe All three outputs are monitored and protected against extreme overloads. A continuous overload on any linear regulator output or an overvoltage on the PWM output disables all converters and drives the FAULT pin to VCC. Figure 3 shows a simplified schematic diagram of the logic of the fault. As soon as an overvoltage VSEN1 is detected it will immediately fail the latch. The three overcurrent fault signals also set the sequence fault latch. The comparator indicates when the CSS is fully charged (UP signal) such that during an undervoltage event either the linear output (or FB2 FB3) will be ignored until the soft start interval (Figure 2). At start-up, this allows VOUT2 and VOUT3 to increase at dead time intervals without faulting. Input bias voltage (+12VINonVCC pin), then turn on reset counter and fault latch.

image 3