An FPGA-based visible light and near-infrared micro-spectrometer, its research scheme and implementation functions are introduced. The miniature spectrometer adopts the MS series CMOS image sensor of Hamamatsu Company, with a wavelength detection range of 340 nm to 1 050 nm and a spectral resolution of about 10 nm; the power consumption is less than 600 mW, and it can be powered directly by USB. Mobile communication, integration time is 5 ms, scan times and integration time are adjustable. Experiments show that the micro-spectrometer has stable output spectral waveform, reliable operation and fast response speed, and can be used in non-destructive testing of agricultural products.
Spectrometer is an important instrument for analyzing the composition of substances. Traditional spectrometers have high precision, but they are bulky and expensive, and have problems such as poor portability and difficulty in popularization in field applications. With the development of miniature opto-electromechanical systems and broadband detectors, miniature spectrometers have been greatly developed [1]. In recent years, commercial miniature spectrometers have emerged one after another. By matching different detectors, broadband and high-precision spectral measurements can be realized. [2]. The miniature spectrometer has high integration, low power consumption, flexibility and convenience, and high cost performance.
1 System design and implementation This miniature spectrometer is mainly composed of complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image sensor, driver and acquisition, Universal Serial Bus (Universal Serial Bus, USB) communication and other modules, the system structure is shown in the figure 1 shown. When the light source illuminates the measured object, diffuse reflection occurs on its surface and shallow layers, and the reflected or transmitted light with internal information is received by the image sensor [4] and transmitted to the Field Programmable Gate Array (FPGA) , after smoothing, and then uploaded to a computer or handheld device via USB for display or further processing [5-8].
The image sensor design adopts MS series CMOS image sensor from Hamamatsu Corporation of Japan. The MS series includes C10822MA-01 (340 nm to 750 nm) and C11708MA (640 nm to 1 050 nm), covering the detection range of visible light and near-infrared. The MS series image sensor includes 256 pixels, the slit size is 75 μm×750 μm, and the pixel size is 12.5 μm×1 000 μm. Its optical structure is a convex blazed grating. 9], reflected on the CMOS sensor, it has a compact structure, a small appearance, a weight of only 9 g, and a low power consumption of only 30 mW. When connecting with a handheld device, low power consumption has a greater advantage.
Hardware circuit design The hardware circuit in this design mainly includes front-end signal processing circuit, analog-to-digital conversion circuit, FPGA minimum system and USB communication circuit [7].
The spectral data output by the CMOS image sensor needs to be filtered by multi-stage buffer amplification and then input to the Analog to Digital Converter (ADC) for conversion. In this design, a three-stage buffer amplifying circuit is used: the first stage follows, the second stage follows The frequency of the analog signal output by the CMOS image sensor is 200 kHz, and the maximum output voltage is 2.76 V. After amplification and filtering, the maximum output voltage can reach 5 V, and the signal-to-noise ratio is significantly improved. AD7671 as an analog-to-digital converter, AD7671 is a 16-bit successive approximation type high-precision analog-to-digital converter, the maximum integral nonlinearity error is ±2.5 LSB (± 190 μV), the sampling rate is up to 1 MS/s, high precision, fast speed , to meet the application requirements. The ADC has three operating modes: Warp, normal and pulse mode. The normal mode is used in this system, and the conversion rate is 800 kS/s. The ADC is configured in master mode to output the previous conversion result during conversion,
The main control chip in the design adopts the EP2C5 T144C8N of ALTERA Company, which has rich logic resources and flexible configuration to meet the design requirements [10]. USB communication adopts CY7C68013 of Cypress Company, which is composed of enhanced 8051 microcontroller with integrated USB2.0 transceiver. Configure the CY7C68013 in Slave FIFO mode in the design. In this mode of USB, the CPU does not participate in data transmission, and is directly transmitted by the internal endpoint, and the endpoint is read and written by the external controller. A schematic diagram of the connection between the FPGA and each module is shown in Figure 6.
The FPGA minimum system and the USB communication circuit are designed according to the chip manual, and finally the PCB board is drawn and made. The 4-layer PCB board size is 45 mm × 84 mm.
Program design FPGA is responsible for the control and transmission of the entire system. The program is written in Verilog HDL language, and the top-down design idea is adopted to design the entire system in blocks [11-12], and finally integrate. The system is mainly divided into three sub-modules [13]: COMS image sensor driver module, AD data buffer module and USB read-write control module. The COMS image sensor driver module is responsible for translating instructions and controlling the working status of the Sensor; the AD cache module is responsible for receiving spectral data, performing smooth filtering processing, and then sending it to the USB read/write module in a time-sharing manner; the USB read/write control module is responsible for sending and receiving data and obtaining the USB state and establish communication [14-15]
The normal use of the CMOS image sensor requires the correct driving timing. In the design, the driving timing is generated by the FPGA. The driving timing must be designed strictly according to the timing of the image sensor. The driving clock of the MS series image sensor is 800 kHz, the output frequency is 200 kHz, and the output frequency is 200 kHz. Completion will give the EOS signal, and the ST signal controls the working state of the sensor. After writing the driver program, it is simulated with ModelSim, and the result shows that the driving sequence meets the design requirements.
The image sensor starts to work after the ST signal arrives and outputs spectral data. The number of scans and the integration time can be controlled by controlling the number of triggers and the trigger cycle of the ST signal in the program [16]. After the spectral analog output is output, it is buffered and amplified, and then AD converted. The CNVST signal is the AD conversion enable signal. The CNVST signal rhythm must be consistent with the sensor output frequency, and the conversion is performed after the waveform is stable. When the CNVST signal arrives, the ADC starts to convert the data. During this period, the previous conversion result is output. When the BUSY signal arrives, the FPGA starts to read the serial data with the SCLK as the clock. After smoothing filtering, the USB read-write module is finally informed that the data is ready, and the USB outputs the data to the host computer [17-18].
The USB read/write module monitors the status of CY7C68013. FLAGA is the empty flag of EP2, and FLAGC is the full flag of EP6. When EP2 is empty, the FPGA will no longer read the FIFO. When EP6 is full, the FPGA will no longer write to the FIFO.
The firmware program is the core of the normal operation of CY7C68013. Cypress company provides the firmware program framework, including fw.c, periph.c, dscr.a51, USBJmptb.OBJ, Ezusb.lib five parts, in this design, mainly for periph. c has been modified to enable EP2 and EP6 endpoints, set the EP2 endpoint to OUT, the buffer size to 512 B, 2 times the cache, the EP6 endpoint to IN, the buffer size to 512 B, 4 times the cache. The endpoints are all block transmission, and the packet is automatically submitted [19-20].
After the system is turned on, the system is first in a standby state, and the Sensor does not work, waiting for the upper computer to send commands. The instruction code is a 16-bit binary number, including integration time, scan times, and default/user-selected bits. The FPGA makes a judgment after receiving the instruction code sent by the upper computer, and then performs the corresponding operation, the Sensor works, and the data is uploaded.
After the host computer is successfully connected, it will enter the mode selection window. In the default mode, the integration time is 100 ms, and the number of transmissions is unlimited. The system will always work and continuously detect the spectrum. In user mode, the integration time and the number of scans can be selected. The minimum number of scans can be selected as 1, the step is 1, and the user can select up to 100 times. The minimum integration time is 5 ms, the maximum is 100 ms, and the step is 5 ms. After the user configures the parameters, the upper computer sends the command to the system, and the system will work according to the set parameters.
In the experiment, an LED desk lamp and a 532 nm laser are used to illuminate the detector head respectively, and the spectrum can be observed on the host computer. This design adopts a system hardware platform with FPGA as the core, combined with MS series CMOS image sensor, to achieve fast and accurate detection of visible light and near-infrared spectrum. The measurement, the spectral data can be transmitted in real time through USB2.0 communication. Experiments show that the miniature spectrometer can accurately measure the spectral wavelength, with good real-time performance; low power consumption, can be directly connected to a mobile phone through USB, and has good portability and practicability; its compact structure and low cost can be widely used.