The ZL2103 is an innovative power conversion and management IC that combines an integrated synchronous buck DC/DC converter with key power management functions in a small package, resulting in a flexible, integrated solution.
The ZL2103 can provide an output voltage of 0.54V to 5.5V (with margin), and the input voltage is between 4.5V and 14V. Internal low RDS(ON) synchronous power MOSFETs enable the ZL2103 to deliver continuous loads up to 3A with high efficiency. Internal Schottky bootstrap diodes reduce discrete component count. The ZL2103 also supports phase expansion to reduce system input capacitance.
Power management functions, such as digital soft-start delay and ramping, sequencing, tracking and fringing, can be configured via simple pin strips or via the on-chip serial port. The ZL2103 communicates with the host controller using the PMBus protocol and uses a digital DC bus for interoperability between other Zilker lab equipment.
Features Integrated MOSFET switch
3A Continuous Output Current ±1% Output Voltage Accuracy Parameter Capture Snapshot
I2C/SMBus interface, PMBus compatible Internal Non-Volatile Memory (NVM)
Telecom, Network, Storage Equipment Test and Measurement Equipment Industrial Control Equipment
5V and 12V distributed power systems

Typical Application Circuit The application circuit below represents a typical implementation of the ZL2103. For PMBus operation, it is recommended to connect the enable pin (en) to SGND.

Ferrite beads are optional for input noise rejection.
The pull-up resistors for the DDC bus will vary depending on the capacitive loading of the bus, including the number of devices connected. Assuming a maximum power of 100 pF per device, the 10 k∑ default provides the necessary 1 microsecond pull-up rise time

ZL2103 Overview of Digital DC Architecture
The ZL2103 is an innovative mixed-signal power conversion and power management integrated circuit based on Zilker Labs patented digital DC technology that provides an integrated high-performance buck converter for point-of-load applications. The ZL2103 integrates all necessary PWM control circuits and low rds(on) synchronous power MOSFETs to provide a very small solution for supplying load currents up to 3A.
Its unique PWM loop utilizes an ideal combination of analog and digital modules, enabling precise control of the entire power conversion process without the need for software, resulting in a very flexible device that is also very easy to use. The extensive power management feature set is fully integrated and can be configured using simple pin connections. User configurations can be saved in internal non-volatile memory (NVM). Additionally, all functions can be configured and monitored via the smbus hardware interface using standard pmbus commands for maximum flexibility.
Once enabled, the ZL2103 is immediately ready to regulate power and perform power management tasks without programming. Advanced configuration options and real-time configuration changes are available via the I2C/SMBus interface if required, and multiple operating parameters can be continuously monitored with minimal interaction from the host controller. The integrated secondary regulation circuit enables single-supply operation from any external supply between 4.5 volts and 14 volts, eliminating the need for a secondary bias supply. The ZL2103 can also be configured to operate from a 3.3V or 5V backup supply when the main power rail is not present, allowing the user to configure and/or read diagnostic information from the device when the main power supply is interrupted or disabled.
The ZL2103 can be configured by simply connecting its pins according to the table provided in the following section. In addition, a comprehensive set of application notes is provided to help simplify the design process. An evaluation board is also available to help users become familiar with the device. The board can be evaluated as a standalone platform using the pin configuration settings. A Windows 8482 ; based graphical user interface is also provided, enabling complete configuration and monitoring functions through the I2c/SMBus interface using an available computer and the included USB cable.
Power Conversion Overview
The ZL2103 adopts a voltage mode, synchronous buck converter, and can choose a constant frequency pulse width modulation (PWM) control scheme. The ZL2103 integrates dual low RDS(ON) synchronous MOSFETs to minimize circuit footprint.
Basic synchronous buck converter topology showing major powertrain components. This converter is also called a buck converter because the output voltage must always be lower than the input voltage.

ZL2103 integrates two N-channel power MOSFETs; QH is the highest control MOSFET and QL is the lowest synchronous MOSFET.
During time d, QH is turned on and VIN–VOUT is applied to the inductor. The output current rises as shown in Figure 11.
When QH is turned off (time 1-d), the current in the inductor must continue to flow from ground up through QL, during which time the current drops. Because the output capacitor exhibits low impedance at the switching frequency, the AC component of the inductor current is filtered out of the output voltage, so the load sees almost a DC voltage.
Max conversion. Typically, Buck converters are specified with a maximum duty cycle, effectively limiting the maximum output voltage achievable for a given input voltage and switching frequency. This duty cycle limit ensures that the low-side MOSFET is allowed to turn on for the minimum amount of time during each switching cycle, allowing the bootstrap capacitor to charge and providing sufficient gate drive voltage for the high-side MOSFET.

Inductance Waveform In general, the size of components l1 and cout and the overall efficiency of the circuit are inversely proportional to the switching frequency fsw. Therefore, the most efficient circuit can be achieved by switching the MOSFETs at the lowest possible frequency; however, this will result in the largest component size. Conversely, the smallest possible footprint can be achieved by switching at the fastest possible frequency, but this reduces efficiency. When determining the switching frequency for each application, each user should determine the best combination of size and efficiency.
The block diagram of ZL2103 is shown in Figure 10. In this circuit, the target output voltage is regulated by connecting the VSEN pin directly to the output regulation point. The VSEN signal is then compared to an internal reference voltage set by the user to the desired output voltage level. The error signal obtained by this comparison is converted into a digital value by an analog-to-digital (A/D) converter. The digital signal is also applied to an adjustable digital compensation filter, which is used to drive the appropriate PWM duty cycle of the internal MOSFET in a way that produces the desired output.
Power Management Overview
The ZL2103 integrates a range of configurable power management functions that can be easily implemented without additional components. In addition, the ZL2103 features circuit protection that continuously protects equipment and loads from damage caused by unexpected system failures. The ZL2103 continuously monitors input voltage, output voltage/current and internal temperature. A power good output signal is also included to enable the power-on reset function of the external processor.
All power management functions can be configured using pin configuration techniques or through the I2c/SMBus interface. Monitoring parameters can also be preconfigured to provide alerts for specific situations. See application note AN2033 for more details on smbus monitoring.
Multimode Pins To simplify circuit design, the ZL2103 features patented multimode pins that allow users to easily configure many aspects of the device without programming. Most power management functions can be configured using these pins. Multimode pins can respond to four different connections, as shown in Table 1. These pins are sampled when power is applied or when the pmbus restore command (see application note AN2033) is issued.
Strap Setup This is the easiest method as no additional components are required. Using this method, each pin can accept one of three possible states: low, on, or high. These pins can be connected to the V2P5 pin for a logic high setting since this pin provides a regulated voltage higher than 2V. Use a single pin to select one of three settings.

Resistor Setting This method allows a larger adjustable range when a finite value resistor (within the specified range) is connected between the multimode pin and SGND.
Using the standard 1% resistor values and using only every fourth E96 resistor value allows the device to reliably identify the resistor value connected to the pin while eliminating errors associated with resistor accuracy. Using one resistor provides up to 31 unique options.
IC/SMBUS Method 2
ZL2103 functions can be configured through the I2c/SMBus interface using standard PMBus commands. Additionally, any value configured using the pin strip or resistor setup method can also be reconfigured and/or verified via I2C/SMBUS. See application note AN2033 for more details.
smbus device address and vout_max are the only parameters that must be set by external pins. All other device parameters can be set via I2C/SMBus. The device address is set using the sa pin. Vout_max is determined to be 10% higher than the voltage set by the VSET pin.
Resistor pin strips are recommended for all available device parameters for a safe initial power-up prior to storing the configuration via I2C/SMBus. This can be accomplished, for example, by fixing the undervoltage lockout threshold (using the ss-pin) to a value greater than the expected input voltage, preventing the device from enabling until the configuration file is loaded.
Power Conversion Functional Description Internal Bias Regulator and Input Power Connections
The ZL2103 uses three internal low dropout (LDO) regulators to bias the internal circuitry, enabling it to operate from an input supply. The internal bias regulators are as follows:
VR: The VR LDO provides a regulated 7V bias power supply for the high-side MOSFET driver circuit. It is powered by the VDDS pin and provides bias current internally. A 4.7µF filter capacitor is required at the VR pin. The VDDS pin directly powers the low-side MOSFET driver circuit.
VRA: The VRA LDO provides a regulated 5V bias supply for current sense circuits and other analog circuits. It is powered by the VDDS pin and provides bias current internally. A 4.7µF filter capacitor is required at the VRA pin.

V2P5: The V2P5 LDO provides a regulated 2.5 V bias supply for the main controller circuit. It is powered by the VRA LDO and provides bias current internally. A 10µF filter capacitor is required on the V2P5 pin.
The VR and VRA pins should not be connected to any other pins when the input supply (VDDS) is above 7.5V. Only one filter capacitor can be connected to these pins. Due to the voltage drop associated with VR and VR bias regulators, the VDDS pin must be connected to these pins for designs operating below 7.5 volts. Figure 13 illustrates the connections required in all cases.
Note: The internal bias regulators, VR and VRA, are not outputs designed to power other circuits. Do not connect external loads to any of these pins. Only multimode pins can be connected to the V2P5 pin for logic high settings.
The gate drive voltage for the high-side MOSFET driver of the high-side driver boost circuit is generated by the floating bootstrap capacitor CB. When the lower MOSFET (QL) is turned on, the sw node is pulled to ground and the capacitor is charged from the internal vr bias regulator through the diode db. When ql is off and the upper MOSFET (qh) is on, the sw node is pulled to vddp and the voltage on the bootstrap capacitor is boosted to about 6.5 V above vddp to provide the necessary voltage to power the high side drivers. Internal Schottky diodes are used with CB to help maximize the high side drive supply voltage Output voltage selection The output voltage can be set to any voltage between 0.6V and 5.0V, provided the input voltage is higher than the desired output voltage, and sufficient to prevent the device from exceeding its maximum duty cycle specification. Using the pin-strap method, VOUT can be set to one of three standard voltages

Stainless steel pin resistor connections Soft-start delay and ramp time can also be set to custom values via the I2C/SMBus interface. When the SS delay time is set to 0ms, the device will start to climb after the internal circuit is initialized (about 2ms). When the soft-start ramp period is set to 0 ms, the output will ramp up quickly as the output load capacitance and loop settings allow. It is generally recommended to set the soft-start ramp to a value greater than 500 microseconds to prevent unexpected failures due to excessive inrush currents.
Power Good (PG)
The ZL2103 provides a Power Good (PG) signal indicating that the output voltage is within the specified tolerance of its target level and that no fault conditions exist. By default, the PG pin will be asserted if the output is within +15%/-10% of the target voltage. These limits can be changed via the I2c/SMBus interface. See application note AN2033 for details.
The pg latency period is the time from when all the conditions for asserting the pg are met until the pg pin is actually asserted. This function is typically used in place of an external reset controller to signal the target voltage of the power supply before enabling any powered circuits. By default, the ZL2103 PG delay is set to 1ms, which can be changed using the I2C/SMBus interface described in AN2033.
Switching Frequency and Phase Locked Loop
The ZL2103 integrates an internal phase-locked loop (PLL) to clock the internal circuits. The PLL can be driven by an external clock source connected to the sync pin. When using the internal oscillator, the sync pin can be configured as a clock source for other Zilker Labs devices.
A sync pin is a unique pin that can perform multiple functions depending on how it is configured. The cfg pin is used to select the operation mode of the sync pin

Configuration A:
When the sync pin is configured as an output (cfg pin is held high), the device will run from its internal oscillator and drive the resulting internal oscillator signal (preset at 400kHz) onto the sync pin so that Other devices can sync with it. In this mode, the sync pins are not checked for incoming clock signals.
Configuration B:

Sync Pin Configuration When a sync pin is configured as an input (CFG pin connected low), the device will automatically check for an external clock signal on the sync pin each time the EN pin is asserted. The internal oscillator will then be synchronized to the rising edge of the external clock. The incoming clock signal must be in the range of 200kHz to 1MHz with a minimum duty cycle and must be stable when the en pin is asserted. The external clock signal must also exhibit the necessary performance requirements (see the "Electrical Specifications" table starting on page 6).
In the event of loss of external clock signal, the output voltage may show transient over/undershoot. If this happens, the ZL2103 will automatically switch to its internal oscillator and switch at a frequency close to the previous input frequency.
Configuration C: Sync Auto Detect When the sync pin is configured in auto detect mode (cfg pin remains open), the device will automatically check the clock signal on the sync pin when enabled. If a valid clock signal is present, the ZL2103's oscillator will be synchronized to the rising edge of the external clock (see synchronization input description).
If no clock signal is input, the ZL2103 will configure the switching frequency according to the state of the sync pins listed in Table 8. In this mode, the ZL2103 only reads the sync pin connections during startup. Changes to the sync pin connections will not affect the FSW until the power supply (VDD) is cycled off and on again.

Component selection
The ZL2103 is a synchronous buck converter with integrated MOSFETs that uses external inductors and capacitors to perform the power conversion process. Proper selection of external components is critical to optimizing performance.
To select the appropriate external components for the desired performance goals, the power requirements listed in Table 10 must be defined.

Bootstrap Capacitor Selection The high-side driver boost circuit utilizes an internal Schottky diode (DB) and an external bootstrap capacitor (CB) to provide adequate gate drive for the high-side MOSFET driver. The circuit breaker should be a 47nF ceramic type with a voltage rating of at least 10V.
CSelect V2P5
This capacitor is used to stabilize the 2.5V internal power supply and provide noise filtering. It should be between 4.7µF and 10µF, should use a semi-stable X5R or X7R dielectric ceramic, have low ESR (less than 10M≠), and should have a 4V rating or higher.
C select VR This capacitor is used to stabilize the 7V reference supply and provide noise filtering. It should be between 4.7µF and 10µF, a semi-stable X5R or X7R dielectric ceramic capacitor should be used, have low ESR (less than 10M≠), and should have a 10V rating or higher. Because the bootstrap supply current is drawn from this capacitor, the magnitude of CVR should be at least 10 times the value of CB so that the discharged CB does not cause an excessive drop in voltage across it during the CB charge pulse.
CSelect VRA
This capacitor is used for stabilization and to provide noise filtering for the analog 5V reference supply. It should be between 2.2µF and 10µF, a semi-stable X5R or X7R dielectric ceramic capacitor should be used, have a low ESR (less than 10M≠), and should have a 6.3V rating or higher.
Thermal Factors In typical applications, the high efficiency of the ZL2103 will limit the power dissipation inside the package. However, in applications requiring high ambient operating temperatures, the user must perform some thermal analysis to ensure that the maximum junction temperature of the ZL2103 is not exceeded.
The ZL2103 has a maximum junction temperature limit of +125°C, and an internal overtemperature limit circuit will force the device to shut down when the junction temperature exceeds this threshold. In order to calculate the maximum junction temperature, the user must first calculate the power dissipated inside the IC (PQ) as shown in Equation 11: P Q2 I load RDS on QHDRDS on QLD
The maximum operating junction temperature can then be calculated using Equation 12: TJ max θ (Equation 12) T pcb p QJC
where tpcb is the expected maximum printed circuit board temperature and θ is the zl2103 package's connection-to-case thermal resistance. JC
Current Sense and Current Limit Threshold Selection
The ZL2103 employs a patented "lossless" current sensing method through an internal low-side MOSFET that is independent of RDS(on) changes (including temperature). The default value of gain (which does not represent the rds(on) value) and the offset of the internal current sensing circuit can be modified by the Output Calibrate Gain and Output Calibrate Offset commands.
The design should include a current limiting mechanism to protect the power supply from damage and prevent excessive current from the input power supply if the output is shorted to ground or an overload condition is applied to the output. Current limit is achieved by inducing current through the circuit for a fraction of the duty cycle. By default, the current limit threshold is set to 4.5a. The current limit threshold can be set to a custom value via the I2c/SMBus interface.
In addition, the ZL2103 provides power supply designers with a choice of fault response under overcurrent or current conditions. The user can select the number of violations allowed before declaring a fault, the blanking time, and the action to take when a fault is detected. Blank time represents the time when no current measurement is made. This is to avoid taking readings after the current loading step (less accuracy due to possible ringing)
loop compensation
ZL2103, as a voltage-type synchronous step-down controller, adopts a fixed-frequency pulse width modulation scheme. Although the ZL2103 uses a digital control loop, its working principle is very similar to a traditional analog PWM controller. Simplified block diagram of the ZL2103 control loop, which differs from the analog control loop only by the constants in the PWM and compensation blocks. As in the case of the analog controller, the compensation block compares the output voltage to the desired reference voltage and adds a compensation zero to keep the loop stable. The resulting integrated error signal is used to drive the PWM logic, converting the error signal to a duty cycle to drive the internal