The DAC7554 is a quad, voltage output DAC with excellent linearity and monotonicity. Its priority structure minimizes unwanted transients such as code-to-code glitches and channel-to-channel crosstalk. The low power DAC7554 runs from a 2.7VT0 5.5 V Py. The DAC7554 0UTPUT amplifier can drive a 2-KL, 200PF load rail-to-rail 5-PS settling time; the output range is set using an external voltage reference.

The 3-wire serial interface operates at a clock rate of T050 MHz and is compatible with SPI, QSPI, Microwire, and DSP interface standards. The outputs of all DACs can be updated simultaneously or sequentially. These parts include a power-on reset circuit to ensure that the DAC output power reaches zero volts and remains there until a valid write cycle to the device occurs. These parts include a power-down feature that reduces the current consumption of the device under LPA.

Section D/A

The architecture of the DAC7554 consists of a DAC in series with an output buffer amplifier. Figure 1 shows an overall block diagram architecture of the DAC. The input code of the DAC7554 is unsigned binary, which gives the ideal output voltage as: VOUT ± REFIN × D/ 4096 where D = decimal equivalent binary code is loaded into the DAC register, which can range from 04095.

Figure 1. Typical DAC Architecture

resistor string

The resistor string section is shown in Figure 2, just a string of resistors, each with a value of R that is determined by the digital code loaded into the DAC register as the voltage of the string on that node is divided to be fed to the output amplifier. This voltage is tapped off to the amplifier by closing the connected switch. Since it is a string resistor, it is monotonic in regulation. The DAC7554 architecture employs four independent resistor strings to minimize channel-to-channel crosstalk.

Figure 2. Typical Resistor String

Output Buffer Amplifier The output buffer amplifier is capable of producing a rail-to-rail voltage at its output, which gives a 0V to V output range DD. It is capable of driving a pair of loads of 2kΩ in parallel up to 1000pF to GND. The capacity of the output source and sink to amplify Ferri can be seen in the typical curves. The output is unloaded with a half-scale settling time of 3 microseconds at a slew rate of 1V/µs.

The DAC external reference input has four digital-to-analog converters with a single reference input pin. The reference input is unbuffered. The user can have a reference voltage as low as 0.25 V and as high as VDD because there is no restriction due to headroom and any reference amplifier footroom. This is the recommended external circuit for a buffered reference. The input impedance is typically 25kΩ.

On power-up, all internal registers are cleared and all channels update zero-scale voltages. All DAC outputs remain in this state until valid data is written. This is especially useful in applications where it is important to know the state of the DAC output when the device is powered up. In order not to put the device under ESD protection, VDD should be applied high on any other pin.

block diagram