The VSP2267 is a complete mixed-signal integrated circuit for CCD signal processing, using a CCD timing generator and A/D converter. The system synchronizes the master clock, HD and VD. The VSP2267 supports all signal termination required for CCD and vertical drivers, as well as externally triggered mechanical shutter and gating functions. The R driver and H driver synchronize the clock phase of the A/D converter to achieve ideal performance. The CCD channel has a correlated double sampling (CDS) function that can extract image information from the CCD output signal. The digitally controlled gain curve is linear in decibels and ranges from -6dB to 42dB. A black level clamp circuit ensures accurate black reference level and fast black level recovery after gain changes. Provides input signal clamping with CDS offset adjustment.
1.2 Features 1.2 Features
The VSP2267 supports the following features:
CCD signal processing:
– Correlated Double Sampling (CDS)
– Programmable Black Level Clamp 8226 ; Timed Generator with R and H Drivers Programmable Phase Control:
– Fine step: 0.6 ns
– Wide step: 8 ns
Programmable Gain Amplifier (PGA): –6 dB to 42 dB gain range
12-bit digital data output:
– Up to 25 MHz conversion rate – No missing codes Signal to noise ratio: 79 dB Portable operation:
– Low voltage: 3.0 V to 3.6 V
– Low power: 138 mW at 3.0 V and 20 MHz
151 mW at 3.0 V and 25 MHz
– Standby plus power save mode: 34 mW – MCLK off mode: 6 mW

The VSP2267 is a high-resolution mixed-signal integrated circuit that contains key functions related to CCD signal processing in digital still cameras (DSCs). The VSP2267 integrates an analog front end (AFE) and a CCD timing generator (TG) with H and R drivers.
The AFE module includes a correlated double sampling (CDS), 14-bit analog-to-digital converter (ADC), digital gain amplifier, black level clamp loop, input clamp, CDS timing generator and voltage reference. The built-in TG can generate not only horizontal (H-rate) timing, but also vertical (V-rate) timing for several specific CCD models. The CCD model and working mode are selected through the serial interface, resulting in optimized timing.
2.2 Timing Generator (TG) 2.2 Timing Generator (TG)
TG produces both H-rate timing and V-rate timing.
TG's high-speed timing block. This section generates six high-speed pulses for H-rate timing, such as R, H1/H2, SHP/SHD, and ADCCK. These high-speed pulses are generated by the master clock, which is twice as fast as the pixel rate. The serial interface sets the amount of phase adjustment for these high-speed pulses in 16 steps (R is 8 steps) with a minimum spacing of 0.6 ns (R is 4 steps, 0.6 ns is 4 steps, and 1.2 ns is 4 steps). Power mode control output driver enable/disable. The on-chip decoder calculates h clear based on the CCD model and operating mode. h1, h2 and r can directly drive the CCD. ADCCK, SHP, SHD, R, H1, and H2 pulses can be selected in internal generation mode or external supply mode.

The V-rate timing generator on the block picture of the VSP2267 high-speed clock circuit generates all the signals required for a particular CCD image sensor. tg contains line and pixel counters used to generate v-rate timings. Figure 2-2 is a block diagram of the line and pixel counter circuit. Timescale supports up to 2047 lines and 4095 pixels per line.
VSP2267 Line and Pixel Counter Circuit Block Diagram

Block diagram of a V-rate timing generator. One hour before the CCD readout (horizontal line), the user must complete the serial data transfer, and the data must be loaded into registers containing information on the CCD model, operating mode, integration time, and electronic zoom area. Before the CCD is read out, the information in the registers is automatically provided to the decoder, which uses the line counter and pixel counter data to generate the V rate signal. Not only the signal for CCD, but also the strobe light control signal is supported. CPOB, CLPD and PBLK can choose internal generation mode or external supply mode.

Analog Front End 2.3 Analog Front End Figure 2-4 shows the simplified AFE block diagram of the VSP2267. The AFE circuit includes correlated double sampling (CDS), 14-bit analog-to-digital converter (ADC), digital gain amplifier, black level clamp loop, input clamp, CDS timing generator and voltage reference. An off-chip emitter follower buffer or preamp is required between the CCD output and the VSP2267 CCDIN input.
VSP2267 AFE Simplified Block Diagram

Correlated Double Sampler (CDS) 2.4 Correlated Double Sampler (CDS)
The output signal of the CCD image sensor is sampled twice during one pixel period: once in the reference interval and once in the data interval. Subtract these two samples, extract the video information of the pixel, remove the low frequency noise KTC and CCD reset noise
The CDS is driven through an off-chip coupling capacitor, C (for C, a 0.1-µF capacitor is recommended). AC coupling is strongly recommended because the DC level of the CCD output signal is often too high (a few volts) for the CD to work properly. A suitable common-mode voltage for CDS is about 0.5 V–1.5 V. The reference level is sampled while the SHP is active, and the voltage level is held on the sampling capacitor C on the trailing edge of the SHP. Data level sampling occurs when the SHD is active, and the voltage level is held on the sampling capacitor C on the trailing edge of the SHD. Subtraction of the two levels is then performed through a switched capacitor amplifier. The off-chip emitter follower or equivalent buffer must be able to drive more than 10 pF, as the 10 pF sampling capacitance is seen at the input. (There is usually some pF of additional stray capacitance.) The analog input signal range of the VSP2267 is about 1vp-p

The CCD output of the input clip buffer is capacitively coupled to the VSP2267. Input clamping restores the DC component of the input signal, which is lost with AC coupling, and establishes the desired DC bias point for CDS. During the dummy pixel interval, the input level is fixed to the internal reference voltage cm (1.5 V)
2.6 14-bit A/D Converter
The ADC uses a fully differential pipeline structure of 1.5 bits per stage, making it ideal for low power, low voltage and high speed applications. The ADC provides 14-bit resolution for the entire scale. The 1.5-bit-per-stage structure of the ADC facilitates better linearity for smaller signal levels. Improved linearity occurs because large linearity errors tend to occur at specific points of full scale, and for signal levels below any such specific point, linearity improves.
2.7 Digital Programmable Gain Amplifier (DPGA)

Characteristics of DPGA gain. The DPGA provides a gain range of –6 dB to 42 dB, linear in dB. Gain is controlled by a digital code with 10-bit resolution and can be set via the serial interface; see the Serial Interface Timing Specification (Section 3) for details. The default value of the gain control code is 128 (PGA gain = 0 dB).
After power up, the gain control value is undefined. Therefore, it must be set to an appropriate value using the serial interface, or reset to default by hitting the SYSRST terminal.

AFE Operation Timing 2.8 AFE Operation Timing
The CDS and ADC are operated by SHP, SHD, and their derived clocks are generated by the internal on-chip timing generator. The DPGA output registers and decoder are operated by ADCCK. The digital output data is synchronized with ADCCK. The timing relationship between the CCD signal, SHP, SHD, ADCCK, and output data is shown in the VSP2267 timing specification. CPOB activates the black level clamping loop during OB pixel intervals, CLPD activates input clamping during dummy pixel intervals.
Black level clamp ring and 10-bit DAC
In order to correctly extract the video information, the CCD signal must be referenced to a mature black level. The VSP2267 has an automatic zero ring (calibration ring) that uses the CCD optical black (OB) pixels to establish the black level. Figure 2-7 shows a block diagram of this loop. The input signal level from the ob pixel is identified as the true black level, and the loop is closed during this time (actually during the time cpob = active). When the auto-zero loop is closed, the difference between the ADC output codes is evaluated and applied to the decoder, which then controls the 10-bit current DAC. The current digital-to-analog converter can charge or discharge an external capacitor at the COB, depending on the sign of the code difference. The loop adjusts the voltage of the COB, thereby setting the offset of the CD so that the code difference is zero. Therefore, during cpob=active, the ADC output code converges to the black level and maintains the black level derived from the ob pixel after the loop has converged. CPOB performs OB clamping of both channels simultaneously.
To determine the loop time constant, an off-chip capacitor is required and should be connected to the COB terminal. The time constant t is calculated with the following formula:
where c is the value of the capacitor connected to COB and i is the minimum current (0.15µA) to control the DAC in the OB level clamp loop, 0.15µA is equivalent to 1 LSB of the DAC output current. When c is 0.1 microF, the time constant t is 40.7 microseconds (the convergence curve becomes exponential) for ADC output codes from 0 LSB to 1543 LSB. Min For output codes above 1543LSB, the current DAC injects a constant (maximum) current into the capacitor, and the convergence curve is linear. Calculate the slew rate sr using the following equation.
where c is the value of the capacitor connected to COB. i is the maximum current of the control DAC in the OB level clamp loop (153 microamps), 153 microamps is equivalent to 1023 LSBs of the DAC output current. Max Normally, OB level clamping at high speed produces clamping noise. However, making C larger can reduce noise. Large Cs, on the other hand, take longer to recover from power saving mode, or immediately after power up. Therefore, 0.1 microF to 0.22 microF is considered a reasonable value for C. If the application environment requires a value outside this range, careful adjustment using trial and error is recommended.
The OB clamp level (base level) is programmable through the serial interface; see the serial interface timing specification for details. See also the Serial Interface Timing Specifications section for the relationship between input codes and OB clamps.
The black level clamp loop removes not only the black level offset of the CCD, but also the offset of the VSP2267 CD and ADC itself.
Pre-Blanking and Data Delay
The VSP2267 has a pre-blanking function. When pblk=low, the digital outputs all go to zero on the ninth rising edge of adcck from the time pblk goes low to accommodate the clock delay of the vsp2267.
The data latency for this device is seven clock cycles. Digital output data appears on the rising edge of ADCCK with a delay of seven clock cycles.
Some CCDs have large transient output signals during the blanking interval. If the input voltage is 0.3 V above the power rails or below the ground rails, the protection diodes are turned on, limiting the input voltage. Such a high swing signal may cause device damage to the VSP2267 and should be avoided.
Power-Saving Mode To save power, the VSP2267 can enter standby plus power-saving mode via serial interface commands. In this mode, all function blocks are disabled, the A/D outputs are all reset to zero, and the TG outputs are put into a high or low state by configuring the serial interface command. Current consumption drops to 34mA. Because all bypass capacitors are discharged in this mode, it takes a considerable amount of time (typically 200-300 ms) to recover from standby plus power save mode.
Additional output delay control
VSP2267 can control the delay time of output data through serial interface setting register. In some cases, the transformation of output data can affect simulation performance. Usually, this is avoided by adjusting the timing of ADCCK. In cases where ADCCK timing cannot be adjusted, additional output delay control can effectively reduce the effects of transient noise. For more information, see Serial Interface Timing Specification.
All reference voltages and bias currents used on voltage reference devices are generated by internal bandgap circuits.
The CDS and ADC mainly use three reference voltages: refp (1.75 V), refn (1.25 V) and cm (1.5 V). refp and refn are buffered on-chip. Cm is derived as the intermediate voltage of the resistor chain connecting refp and refn internally. The ADC full-scale range is determined by twice the voltage difference between refp and refn.

Operation Mode Field mode allows the summation of vertically adjacent pixels.
Frame mode enables per pixel output.
×2 Velocity mode enables output interval lines.
The ×2 monitoring mode can provide 2×8 lines or 2×10 lines of output for CCDS 2A or 2B, respectively.
Field mode, frame mode and x2 speed mode operate interleaved between even/odd frames.
The large function long integrated function stops CCD readings (CH1, CH2, CH3, CH4 pulses) at the end of a frame, as defined by the serial data command.
The power save function stops all clocks and holds them high or low by serial data commands.
The strobe function enables external strobe operation to synchronize electronic shutter timing via serial data commands.
The E-ZOOM function enables electronic zoom to select consecutive lines based on serial data commands.