1. General Instructions
The W681310 is a general-purpose single-channel PCM codec with pin-selectable law or A-law companding. The device complies with the ITU G. 712 specification. It is powered by a +3V supply and is available in 20-pin SOG, SSOP and TSSOP package options. The functions performed include digitization and reconstruction of speech signals, as well as band limiting and smoothing filters required by PCM systems. W681310 performance is specified over the industrial temperature range -40°C to +85°C.
The W681310 includes an on-chip precision voltage reference and an additional power amplifier capable of driving 300 Ω loads in various ways, up to a peak-to-peak voltage level of 3.544V. The analog part is fully differential to reduce noise and improve power supply rejection ratio. The data transmission protocol supports long-frame and short-frame synchronous communication for PCM applications, and IDL and GCI communication for ISDN applications. The W681310 accepts eight master clock rates between 256 kHz and 4.800 MHz, and an on-chip prescaler automatically determines the desired internal clock division ratio.
For quick evaluation and prototyping, the W681310DK development kit is available.

2. Features Single +3V supply (2.7V to 5.25V) 10 mW typical power consumption, 0.5µW in power-down mode Fully differential analog circuit design On-chip accuracy reference of 0.886 V for -5 at 600Ω dBm TLP  Push-pull power amplifier W with external gain adjustment with 300∙ load capability  8 master clock frequencies from 256 kHz to 4.800 MHz  Pin selectable ∙-law and A-law companding (compliant with ITU G.711)  Codec A/D and D/A filtering compliant with ITU G.712  Industrial temperature range (–40°C to +85C)  Packages: 20-pin SOG (SOP), SSOP and TSSOP  Lead-free packaging options available Applications  VOIP, Voice Networks  Digital Telephony and Communication Systems  Wireless Voice Devices  PABX/SOHO Systems  Local Loop Cards  SOHO Routers

Function description
The W681310 is a single-track single-channel PCM codec for soundtrack applications. The codec conforms to the specifications recommended by ITU-T G.712. The codec also includes a full legal and legal firm. Legal and legal firms are designed to comply with the specifications of the ITU-T G.711 recommendation.
Main components of W681310. The chip consists of a PCM interface that can handle long and short frame sync formats as well as GCI and IDL formats. The chip's prescaler provides the internal clock signal and synchronizes the codec sample rate to the external frame sync frequency. The Power Conditioning block provides internal power for the digital and analog sections, and the Voltage Reference block provides an accurate analog ground voltage for analog signal processing. The main codec block diagram is shown in Section 3.
Transmission Path The A to D path of the codec contains an analog input amplifier with externally configurable gain settings. The device has an input op-amp whose output is the input to the encoder section. If the input amplifier is not required for operation, it can be turned off and bypassed. In this case, a single-ended input signal can be applied to the AO pin or the AI pin. When the input amplifier is powered down, the AO pin becomes high input impedance. The input amplifier can be powered down by connecting the AI+ pin to VDD or VSS. AO pin selection is

When the input amplifier is powered off, the input signal at AO or AI- needs to be referenced to the analog ground voltage VAG.
The output of the input amplifier is fed through a 3.4 kHz switched capacitor low-pass filter to prevent aliasing of the input signal beyond 4 kHz due to 8 kHz sampling. The output of the 3.4 kHz low-pass filter is filtered by a high-pass filter with a 200 Hz cutoff frequency. Design the filter according to the recommendations in the G.712 ITU-T specification. The output signal from the high pass filter is digitized. The signal is converted into a compressed 8-bit digital representation, either in μ-law or A-law format. The μ-law or a-law format is selectable via the μ/a-law pin.
At the sampling rate provided by the external frame synchronization fst, the digital 8-bit law or A-law samples are sent to the PCM interface for serial transmission.
receive path
The 8-bit digital input samples of the d-to-a path are serially shifted in by the PCM interface and converted to parallel data bits. During each cycle of the frame sync FSR, parallel data bits are input through a pin-selectable µlaw or a-law expander and converted to analog samples. The dilation mode is selected by the /a-law pin, and the analog samples are filtered through a low-pass smoothing filter with a 3.4 kHz cutoff frequency according to the ITU-T G.712 specification. SIN(x)/x compensation is integrated with a low-pass smoothing filter. The output of the filter is buffered to provide the receive output signal ro-. The RO- output can be connected externally to the PAI pin to provide a differential output with high drive capability at the PAO+ and PAO- pins. Various gain settings for this output amplifier can be achieved by using external resistors (see example in Section 11). If the transmit power amplifier is not in use, it can be turned off by connecting PAI to VDD.
Power Management Analog and Digital Power
The power supply for the analog and digital parts of the W681310 must be 2.7V to 5.25V. This supply voltage is connected to the VDD pin. The VDD pin needs to be separated from ground by a 0.1µF ceramic capacitor.
Analog Ground Reference Bypass This system features an internal precision voltage reference that generates a VDD/2 mid-supply analog ground voltage. This voltage needs to be decoupled from Vss at the Vref pin with a 0.1µf ceramic capacitor.
Analog Ground Reference Output An analog ground reference can be used as an external reference for the VAG pin. This voltage needs to be decoupled to Vss with a 0.01µF ceramic capacitor. The analog ground reference is generated from the voltage on the VREF pin and is also used for internal signal processing.
Pulse code modulation interface
The PCM interface is controlled by pins BCLKR, FSR, BCLKT and FST. Input data is received through the PCMR pin, and output data is transmitted through the PCMT pin.

Long Frame Sync Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the BCLKR or BCLKT pin to a 64 kHz to 4.800 MHz clock, and connecting the FSR or FST pin to an 8 kHz frame sync. The device synchronizes the data word of the PCM interface and the codec sample rate on the positive edge of the frame sync signal. It identifies a long frame sync when the fst pin remains high for two consecutive bit clock falling edges at the bclkt pin. The length of the frame sync pulse can vary from frame to frame, as long as the positive sync edge of the frame occurs every 125 μs. During data transmission in the long frame synchronization mode, when the frame synchronization signal fst is high or an 8-bit data word is transmitted, the transmission data pin pcmt will become low impedance. The transmit data pin pcmt will go high impedance when the frame sync signal fst goes low when data is being transmitted or when half the LSB is being transmitted. The internal decision logic will determine whether the next frame sync is a long frame sync or a short frame sync based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will have high impedance for two frame sync cycles after each power down state. More detailed timing information can be found in the Interface Timing section.
short frame sync
The W681310 operates in short frame sync mode when the frame sync signal at pin fst is up to one and only one falling edge of the BCLKT pin bit clock. On the subsequent rising edge of the bit clock, the W681310 starts clocking data on the PCMT pin, which also changes from a high-impedance state to a low-impedance state. The data transfer pin PCMT will return to a high impedance state in the middle of the LSB. The short frame synchronization operation of the W681310 is based on an 8-bit data word. When data on the PCMR pin is received, the data is clocked on the first falling edge after the falling edge consistent with the frame sync signal. The internal decision logic will determine whether the next frame sync is a long frame sync or a short frame sync based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will have high impedance for two frame sync cycles after each power down state. More detailed timing information can be found in the Interface Timing section.
Generic Circuit Interface (GCI)
GCI interface mode is selected when the BCLKR pin is tied to VSS for two or more frame sync cycles. It can be used as a 2b+d timing interface in ISDN applications. The GCI interface consists of 4 pins: FSC (FST), DCL (BCLKT), DOUT (PCMT) and DIN (PCMR). The FSR pin selects channel B1 or B2 for transmit and receive. Data transitions occur on the positive edge of the data clock DCL. The frame sync positive edge is aligned with the positive edge of the data clock DCLK. The data rate is half the bit clock speed. Channels b1 and b2 transmit continuously. Therefore, channel b1 transmits on the first 16 clock cycles of DCL, and b2 transmits on the second 16 clock cycles of DCL. See the Timing section for more timing information. The GCI interface supports data rates from 256 kHz to 3088 kHz and bit clocks from 512 kHz to 6176 kHz.
Inter-chip digital link (IDL)
The IDL interface mode is selected when the BCLKR pin is tied to VDD for two or more frame sync cycles. It can be used as a 2b+d timing interface in ISDN applications. The IDL interface consists of 4 pins: IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) and IDL RX (PCMR). The FSR pin selects channel B1 or B2 for transmit and receive. Data for channel b1 is transferred to the first positive edge of IDL CLK after the IDL sync pulse. The IDL sync pulse is one IDL CLK period long. Data from channel B2 is transferred to the eleventh positive edge of IDL CLK after the IDL sync pulse. Data for channel B1 is received on the first negative edge of IDL CLK after the IDL sync pulse. Data for channel B2 is received on the 11th negative edge of IDL CLK after the IDL sync pulse. When not used for data transmission, and in time slots of unused channels, the transmission signal pin IDL TX will become high impedance. See the Timing section for more timing information.
System Timing The system can operate at master clock frequencies of 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz, 4096 kHz and 4800 kHz. The system clock is provided through the master clock input MCLK, which can be derived from the bit clock if desired. Internal prescalers are used to generate fixed 256 kHz and 8 kHz sample clocks for the internal codec. The prescaler measures the master clock frequency and frame sync frequency and sets the division ratio accordingly. If the frame sync is low for the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the W681310 will enter a low power standby mode. Another way to power down is to set the PUI pin low. When the system needs to be powered up again, the PUI pin needs to be set high and the frame sync pulse needs to be present. Two frame sync cycles are required before pin PCMT goes low impedance.