The AD420 is a complete digital to current loop output converter designed to meet the needs of the industrial control market. It provides a high-accuracy, fully integrated, low-cost single-chip solution for generating current loop signals in a compact 24-pin SOIC or PDIP package. The output current range is programmable from 4 mA to 20 mA, 0 mA to 20 mA, or 0 mA to 24 mA for the overrange function.

The AD420 can also provide a voltage output from a separate pin that can be configured to provide 0 V to 5 V, 0 V to 10 V, ±5 V or ±10 V, with the addition of an external resistive buffer amplifier. The 3.3 Mbaud serial input logic design minimizes cost with galvanic isolation and can often be easily interfaced to used microprocessors. It can be used in 3-wire or asynchronous mode and the serial output pin is used to allow daisy-chaining of multiple DACs on the current loop side of the isolation barrier.

The AD420 uses sigma-delta (Σ-Δ) DAC technology to achieve 16-bit monotonicity at a very low cost. Full settlement to 0.1% occurs within 3 ms. The only external components required (besides the normal transient protection circuitry) are two low cost capacitors for the DAC output filter. If the AD420 is used at extreme temperatures and supply voltages, an external output transistor can be used to minimize

Power dissipation is implemented on-chip through the BOOST pin. Error The DETECT pin is signaled when an open circuit occurs in the loop.

An on-chip voltage reference can be used to provide accuracy. In addition to the AD420, +5V can be applied to external components. Users want temperature stability in excess of 25 ppm/°C. An external precision voltage reference such as the AD586 can be used as a reference.

The AD420 operates over a -40°C to +85°C temperature range in a 24-lead SOIC and PDIP.

feature:

4 mA-20 mA, 0 mA-20 mA or 0 mA-24 mA current output, 16-bit resolution and monotonicity

±0.012% maximum integral nonlinearity

±0.05% maximum offset (trimmable)

±0.15% maximum total output error (can be fine-tuned)

Flexible Serial Digital Interface (3.3 MBPS)

On-chip loop fault detection

On-chip 5 V reference (25 ppm/°C max)

Asynchronous CLEAR function

The maximum supply range is 32 V.

Output Loop Compliant 0 V to VCC - 2.75 V

24-pin SOIC and PDIP packages

Functional block diagram

Product Highlights:

1. The AD420 is a single-chip solution that generates a 20 mA or 0 mA to 20 mA signal current loop at the 4 mA current controller side.

2. AD420 power supply range is 12 V to 32 V. Output loop compatibility is 0 V to VCC - 2.75 V.

3. Flexible serial input can be used in 3-wire mode using SPI 174 ; or MICROWIRE® microcontrollers, or using asynchronous mode, minimizing the number of control signals needed.

4. The serial data output pins can be used to daisy-chain any number of AD420s together in 3-wire mode.

5. On power-up, the AD420 initializes its output to a low level at the end of the selected range.

6. The AD420 has an asynchronous CLEAR pin that can send the output to the low end of the selected range (0 mA, 4 mA, or 0 V).

7. AD420 BOOST pin can accommodate external pin transistors to reduce the power consumption of the chip.

8. The offset is ±0.05%, and the total output error is ±0.15% If required, it can be trimmed using two external potentiometers.

Pin Configuration and Functional Description

1. VLL auxiliary buffer +4.5 V digital logic voltage. This pin is the digital internal supply voltage circuit and can be used as a termination for pull-up resistors. An external +5 V power supply can be connected to the VLL. It will override this buffer voltage, reducing internal power dissipation. The VLL pin should be decoupled to GND with a 0.1µF capacitor. See the Power and Decoupling section.

2. Fault detection Fault detection is connected to a pull-up resistor and is set low to the programmed value of the DAC when the output current does not match, for example, in the case of a current loop disconnected.

3. RANGE SELECT 2 selects the output operating range of the converter. one output voltage range and three

4. RANGE SELECT 1 output current range is available.

5. CLEAR valid VIH unconditionally forces the output to reach the minimum value of its programming range. Removing the DAC output after CLEAR will maintain this value. The data in the input registers is not affected.

6. LATCH In 3-wire interface mode, the rising edge loads the serial input register data into the DAC in parallel. To use asynchronously connect LATCH to VCC through a current limiting resistor.

7. Clock data clock input. The clock period is equal to the input data bit rate in 3-wire interface mode 16 times the bit rate in asynchronous mode.

8. Serial data input data.

9. DATA OUT serial data output. In 3-wire interface mode, this output can be used to daisy-chain multiplex AD420s. In asynchronous mode, a positive pulse will indicate frame error reception after the stop bit.

Three-wire interface on digital lines Fast edge INPUT One of the serial inputs has a fast rising edge (<100 ns)

(CLOCK, DATA IN, LATCH) while the other input is logic high, the part may be triggered into test mode and the contents of the data register may be corrupted, which may cause the output to be loaded with an incorrect value. If a fast edge is expected on a digital input line, it is recommended that the latch line be held at logic 0 during serial loading of the DAC. Also, during the update, the clock line should be held low to DAC through the latch pin. Alternatively, adding a small value of capacitance on the digit line will slow down the edges.

Asynchronous interface

Note that in the timing diagram for asynchronous mode operation, each data word consists of a START (0) bit followed by a STOP frame (1) bit. Data timing is relative to the rising edge of CLOCK at the center of each bit cell. The bit unit is a 16 clock long, and the first unit (START bit) follows the leading edge (falling edge) of the START bit from the first clock. So MSB ( D15 ) samples the START bit 24 clock cycles after the start, D14 samples at clock number 40, and so on. The IN pin must be held at logic 1 for any dead time before writing the next word DATA. When a STOP bit is received, the DAC output is updated. In the case of a frame error (the STOP bit is sampled as 0) the AD420 will output a cycle-wide STOP bit within the clock cycle after the DATA OUT pin is sampled with a clock pulse. If framing, the DAC output will not update if an error is detected.

Resolution: For 16-bit resolution, 1 LSB = 0.0015% of the FSR. In the 4 mA-20 mA range 1 LSB = 244 nA. Integral Nonlinearity Analog Devices defines integral nonlinearity as the maximum actual adjusted DAC output deviation from the ideal analog output (straight line from 0 to FS - 1 LSB) for any combination of bits. This is also called relative accuracy.

Differential Nonlinearity: Differential nonlinearity is a measure of change in the analog output, normalized to full scale, and correlated with the LSB to change the digital input code. Monotonic behavior requires a differential linearity error greater than -1 LSB over the temperature range of interest.

Monotonicity: The DAC is a monotonic constant increasing digital input if the output increases or remains, the result is that the output will always be a single-valued function of the input.

Gain Error: Gain error measures the output error between the ideal value of the DAC and the actual device output, loaded with all 1s after the offset error has been adjusted out.

Offset Error: Offset error is the deviation of the output current from the ideal value expressed as a percentage of full-scale output with 0 loaded in the DAC.

Drift: Drift is the change in parameters such as gain and offset over a specified temperature range. Drift temperature coefficient, expressed in ppm/°C, is calculated by measuring the parameters at TMIN, 25°C and TMAX and dividing by the change in the parameter by the corresponding temperature change.

Current Loop Voltage Compliance: Voltage compliance is the maximum voltage at the IOUT pin that the output current will be equal to the programmed value.

Theory of Operation

The AD420 uses a sigma-delta (Σ-Δ) architecture for digital-to-analog conversion. This architecture is especially well suited for relatively low bandwidth demanding industrial control environments due to its inherent high-resolution monotonicity.

In the AD420, a second-order modulator is used to minimize complexity and chip size. A single-bit stream modulator from a switched current source is partially filtered by two continuous-time resistor-capacitors. Capacitors are the only external components necessary to add standard current output operation. The filtered current is amplified and mirrored to the supply rails so that the application only needs to see the 4 mA-20 mA, 0 mA-20 mA, or 0 mA-24 mA current source output relative to ground. The AD420 is fabricated in a BiCMOS process and is ideal for implementing high-performance low-voltage digital logic and high-voltage analog circuits.

The AD420 can also provide a voltage output instead of a current loop output if desired. The addition of an external amplifier allows the user to obtain 0 V-5 V, 0 V-10 V, ±5 V or ±10 V.

The AD420 has a loop fault detection circuit that warns that the voltage at IOUT attempts to exceed the compliance range of the open loop circuit or that the supply voltage is insufficient. The fault detection is a valid low open-drain signal, so one can connect several AD420s to a single pull-up resistor for global error detection. Pull-up resistors can be connected to the VLL pin or to an external +5 V logic supply. The IOUT current is controlled by a PMOS transistor with an internal amplifier as shown in the functional block diagram. The internal circuitry that generates the fault output avoids the use of comparators with window limits, as this requires the actual output error to become active before the FAULT DETECT output. Conversely, the internal amplifier of the AD420 output stage has less than about 1 volt of drive capability remaining when the signal is generated when the gate of the output PMOS transistor almost reaches ground. Therefore, the FAULT DETECT output activates slightly before reaching the compliance limit. Since the comparison is made within the feedback loop of the output amplifier, the output maintains accuracy through the open loop gain, and no output error occurs until the fault detection output becomes active. 3-wire digital interfaces, including DATA IN, CLOCK, and LATCH, connect all commonly used serial microprocessors without adding any external glue logic. Data is loaded into the input register under the control of CLOCK

Loaded to DAC when LATCH is strobe. If the user wants to substantially reduce the number of galvanic isolators for safety applications, the AD420 can be configured to operate in asynchronous mode. Select this mode by connecting the LATCH pin to VCC through a current limiting resistor. data

It must then be combined with start and stop bits to build the frame information and trigger the internal LATCH signal.

The AD420 can provide 4 mA-20 mA, 0 mA-20 mA, or 0 mA-24 mA output without any active external components. Filter capacitors C1 and C2 can be any type of low cost ceramic capacitors. To meet the specified full-scale settling time of 3 ms, a low dielectric absorption capacitor (NPO) is required. Suitable values are C1 = 0.01 μF and C2 = 0.01 μF.

Standard configuration diagram

Drive inductive loads

When driving an inductive or ill-defined load, connect a 0.01µ capacitor between FIOUT (Pin 18) and GND (Pin 11). This ensures the stability of the AD420 with loads exceeding 50 mH. There is no maximum capacitance limit. Capacitive element loading may result in slower settling, but this may mask the settling time of the AD420. A programmed change in current may cause a back-EMF voltage at the output beyond the compliance of the AD420. To prevent this voltage from exceeding the supply rails connect protection diodes

between IOUT and each VCC and GND.

Voltage Mode Output

Since the AD420 is a single-supply device, an external buffer amplifier needs to be added to the VOUT pin to select the bipolar output voltage range as shown in the figure below.

Optional span and zero trim

For user offset and gain errors that you want to be below specified values, the following figure shows a simple way to trim these parameters. Care should be taken to choose low drift resistors as they will affect the temperature drift performance of the DAC. The tuning algorithm is iterative. The program can adjust the AD420 in the 4 mA-20 mA mode

Complete as follows:

1. Offset adjustment. Load all zeros. Adjust RZERO4.00000 mA output current.

2. Gain adjustment. Load all. Adjust RSPAN to 19.99976 mA (FS - 1 LSB) output current. Return to step I and iterate until convergence is obtained.

RZERO change offset adjustment between REF OUT (5 V) and GND leads from -1.5 mA to 6 mA (1.5 mA/V.

Centered at 1 V. A 5kΩ RSPAN2 resistor in parallel with the internal 40 W sense resistor results in a +0.8% gain increase. When RSPAN becomes 500 Ω, the voltage on REF IN is attenuated by the combined input resistance of RSPAN and 30kΩ REFIN. Results adjustment ranged from -0.8% to +0.8% when added with RSPAN2.

three-wire interface

The figure below shows the AD420 mode connected with a 3-wire interface. The AD420 data input module contains a serial input shift register and parallel latches. The contents of the shift register are clocked by the DATA IN signal and the rising edge. The DAC and internal latches are updated in parallel from the shift register as requested by the LATCH pin. CLOCK should remain inactive while it is time to update the DAC.

Multiple DACs can be easily connected using the serial data output using the Multiple DAC 3-Wire Interface Mode with Fault Detection. To program two AD420s in the picture above, 32 data bits are required. The first 16 bits are clocked into the input shift register of DAC1. The next 16 bits are sent through the first 16 bits of the DATA OUT pin to the input registers of DAC1 to DAC2. Input Shift Register The two DACs operate as a single 32-bit shift register, with leading 16 bits representing information for DAC2 and DAC2 trailing 16 bits for DAC1. Then update each DAC according to the requirements of the LATCH pin. The daisy chain can be extended to as many DACs as needed.

Asynchronous interface usage

The optocoupler AD420 is connected to the optocoupler in asynchronous interface mode as shown in the figure below. Asynchronous operation minimizes the number of control signals required to isolate the digital system from the control loop. Connecting a resistor is required between the LATCH pin and VCC to activate this mode. For operation with VCC below 18 V, use a 50kΩ pull-up resistor; from 18 V to 32 V, use 100kΩ.

Asynchronous mode requires the clock to run at 16 times the speed. Therefore, a 2.4 MHz input clock is required when the data bit rate is running at the maximum input data rate of 150 kBPS. The actual data rate achieved may be chosen limited by the type of optocoupler. The number of control signals can be further reduced by creating appropriate clock signal isolation barriers on the current loop side. If the optocoupler is relatively slow using rise and fall times, a Schmitt trigger digital input may be required to prevent erroneous data from being presented to the DAC.