Function description
8-Channel Voltage Controlled Amplifier – LNA, VCAT, PGA, LPF and CW Mixer The VCA5807 is an integrated voltage controlled amplifier (VCA) designed for high performance, small form factor ultrasound systems.
Programmable Low Noise Amplifier (LNA)
24/18/12 dB gain
-0.25/0.5/1 Vpp linear input range
-0.63/0.7/0.9 nv/rthz input referred noise
- Programmable active termination
40dB Low Noise Voltage Controlled Attenuator (VCAT)
24/30dB Programmable Gain Amplifier (PGA)
Third Order Linear Phase Low Pass Filter (LPF)
-10, 15, 20, 30 MHz
- Butterworth character

Noise/Power Optimization (Full Chain)
-99 mw/ch at -0.75 nv/rthz
56 mw/ch at -1.1 nv/rthz
- 80 mW/ch in CW mode
Excellent inter-device gain matching
-±0.5 dB (typ.) and ±1.05 dB (max.)
Low Harmonic Distortion Fast Consistent Overload Recovery Low Frequency Sonar Signal Processing Continuous Wave Doppler Passive Mixer (CWD)
- Low closed phase noise – 156 dBc/Hz at 1
kHz off 2.5 MHz carrier
- Phase resolution 1/16λ
- Supports 32x, 16x, 8x, 4x and 1x CW clocks
-12dB rejection of 3rd and 5th harmonics
- Flexible input clock
14mm x 14mm, 100-pin TQFP
Sonar imaging with non-destructive evaluation equipment for medical ultrasound imaging is required. The VCA5807 integrates a complete Time Gain Control (TGC) imaging path and a Continuous Wave Doppler (CWD) path. It also allows the user to select one of various power/noise combinations to optimize system performance. Therefore, VCA5807 is not only suitable for high-end systems, but also suitable for portable systems, is a suitable ultrasound analog front-end solution.
The VCA5807 contains an eight-channel voltage-controlled amplifier (VCA) and a continuous-wave mixer. The VCA includes a low noise amplifier (LNA), a voltage controlled attenuator (VCAT), a programmable gain amplifier (PGA) and a low pass filter (LPF). The LNA gain is programmable to support 250 mvpp to 1 vpp input signals. The LNA also supports programmable active termination. The ultra-low noise VCAT provides a 40dB attenuation control range, improving the overall low-gain signal-to-noise ratio, which is beneficial for harmonic imaging and near-field imaging. The PGA offers gain options of 24dB and 30dB. Before the ADC, the LPF can be configured at 10 MHz, 15 MHz, 20 MHz, or 30 MHz to support ultrasound applications at different frequencies. In addition, the VCA5807's signal chain can handle signal frequencies below 100kHz, which makes it useful not only for ultrasonic applications, but also for sonar applications.
The VCA5807 integrates a low-power passive mixer and a low-noise sum amplifier to implement a single-chip CWD beamformer. 16 selectable phase delays can be applied to each analog input signal. At the same time, the unique third-order and fifth-order harmonic suppression filters are used to improve the sensitivity of continuous waves.
The VCA5807 is available in a 14mm x 14mm, 100pin TQFP package, which is specified for -40°C to 85°C operation.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits can be more susceptible to damage because very small parameter changes can cause the device to not meet its published specifications.

The programming of register writing describing different modes can be done through the serial interface consisting of pins sen (serial interface enable), sclk (serial interface clock), sdata (serial interface data) and reset. All of these pins have a pull-down resistor of 20kΩ to ground. When SEN is low, bit-to-device serial shifting is enabled. When SEN is active (low), serial data SData is latched on every rising edge of SCLK. When SEN is low, serial data is loaded into the register on every 24th SCLK rising edge. If the word length exceeds a multiple of 24 bits, the extra bits are ignored. Data can be loaded in multiple words of 24-bit words within a single active SEN pulse (there is an internal counter that counts groups of 24 clocks after the falling edge of SEN). The interface can operate at SCLK frequencies from 20 MHz to low speed (several Hz), and even at non-50% duty cycle SCLKs. The data is divided into two main parts: the register address (8 bits) and the data itself (16 bits), loaded onto the address register. When writing to a register with unused bits, these bits should be set to 0.

Register readout indicates that the device includes an option in which the contents of internal registers can be readout. This may help with diagnostic tests to verify serial interface communication between the external controller and the VCA. first, The bit (reg0[1]) needs to be set to "1". The user should then initiate a serial interface loop specifying the address of the registers (A7-A0) whose contents must be read. The data bits are "don't care". The device will output the contents of the selected register (d15-d0) on the sdout pin. The typical delay t8 for sdout is 20 ns from the falling edge of SCLK. For low-speed SCLK, SDOUT can be latched on the rising edge of SCLK. For high-speed SCLK, that is, when the SCLK period is less than 60ns, it is best to lock SDout on the next falling edge of SCLK.

VCA register description
LNA input impedance configuration (active termination programmability)
Different LNA input impedances can be configured through Register 52[4:0]. By enabling and disabling the feedback resistor between the LNA output and the ACTX pin, the LNA input impedance can be adjusted accordingly. The relationship between the LNA gain and the 52[4:0] setting. The input impedance settings for the TGC and CW paths are the same.
The VCA5807 also has 4 preset active termination impedances as described in 52[7:6]. An internal decoder is used to select appropriate resistors for different LNA gains.
The VCA5807 is an integrated voltage-controlled amplifier (VCA) solution designed for ultrasound systems that require high performance and small size. The VCA5807 integrates a complete Time Gain Control (TGC) imaging path and a Continuous Wave Doppler (CWD) path. It also allows the user to select one of various power/noise combinations to optimize system performance. The VCA5807 contains eight channels; each channel includes a low noise amplifier (LNA), voltage controlled attenuator (VCAT), programmable gain amplifier (PGA), low pass filter (LPF) and continuous wave mixer.
In addition, several features in the VCA5807 are suitable for ultrasonic applications such as active termination, single channel control, fast power up/down response, programmable clamp voltage control, fast and consistent overload recovery and turn-on. As a result, the VCA5807 brings premium image quality to ultra-portable handheld systems all the way to high-end ultrasound systems. Additionally, the VCA5807 can support sonar applications, considering its excellent low frequency (<100 kHz) response.

Low Noise Amplifier (LNA)
In many high-gain systems, a low-noise amplifier is the key to achieving overall performance. Using a new proprietary architecture, the LNA in the VCA5807 provides excellent low noise performance while operating at very low quiescent current compared to CMOS-based architectures with similar noise performance. The LNA performs single-ended input to differential output voltage conversion. It is configurable for programmable gains of 24/18/12db, and its input-referred noise is 0.63/0.70/0.9nv/√hz, respectively. Programmable gain settings enable linear input ranges to 1vpp, enabling the high signal processing capabilities required by new sensor technologies. Larger input signals can be accepted by the LNA; however, as the signal exceeds the LNA's linear operating region, the signal may be distorted. Combined with low noise and high input range, a wide input dynamic range is achieved, meeting the high requirements of various ultrasound imaging modalities.

Low Noise Amplifier (LNA)
In many high-gain systems, a low-noise amplifier is the key to achieving overall performance. Using a new proprietary architecture, the LNA in the VCA5807 provides excellent low noise performance while operating at very low quiescent current compared to CMOS-based architectures with similar noise performance. The LNA performs single-ended input to differential output voltage conversion. It is configurable for programmable gains of 24/18/12db, and its input-referred noise is 0.63/0.70/0.9nv/√hz, respectively. Programmable gain settings enable linear input ranges to 1vpp, enabling the high signal processing capabilities required by new sensor technologies. Larger input signals can be accepted by the LNA; however, as the signal exceeds the LNA's linear operating region, the signal may be distorted. Combined with low noise and high input range, a wide input dynamic range is achieved, meeting the high requirements of various ultrasound imaging modalities.
The internal bias of the LNA input is approximately +2.4V; the signal source should be AC coupled to the LNA input through an appropriately sized capacitor (ie, ≥0.1 µF). To achieve low DC offset drift, the VCA5807 integrates a DC offset correction circuit for each amplifier stage. In order to improve the overload recovery rate, an integrator circuit is used to extract the DC component of the output of the LNA, and then feed it back to the complementary input of the LNA for DC offset correction. The DC offset correction circuit has a high-pass response and can be processed as a high-pass filter. The effective angular frequency is determined by the capacitor cBypass connected in inm. The larger the capacitor, the lower the corner frequency. For stable operation at the highest high-voltage filter cutoff frequency, choose a capacitor ≥15nF. This angular frequency is almost linearly proportional to the value of cBypass. For example, 15nf gives a corner frequency of about 100kHz, while 47nf gives an effective corner frequency of 33kHz. The DC offset correction circuit can also be disabled/enabled via Register 52[12] if low frequency operation is required. A large capacitor (such as 1 microF) can be used to set the low corner frequency (<2 kHz) of the LNA DC offset correction circuit.
The VCA5807 can be passively or actively terminated. Active termination is preferred in ultrasonic applications to reduce mismatched reflections and achieve better axial resolution without unduly degrading noise figure. Active termination values can be preset to 50, 100, 200, 400Ω; other values can also be programmed by the user through Register 52[4:0]. A feedback capacitor is required between actx and the signal source, and on the active termination path, a clamp circuit is also used to create a low impedance path when the VCA5807 sees an overloaded signal. The clamp circuit limits the large input signal at the input of the LNA, improving the overload recovery performance of the VCA5807. When register 52[10:9]=0, the clamp level can be automatically set to 350mvpp, 600mvpp, 1.15vpp according to the LNA gain setting. Other clamp voltages, such as 1.15Vpp, 0.6Vpp, and 1.5Vpp, can also be achieved by setting Register 52[10:9]. This clamp circuit design also achieves good pulse inversion performance and reduces the effects of asymmetric inputs. Note that the clamp settings may change during LNA gain switching. Therefore, the fixed time of the clamping must be considered when adjusting the LNA gain, especially when the overload signal exceeds the clamping voltage.

Voltage-Controlled Attenuators Voltage-controlled attenuators are designed to have a linear In-dB attenuation characteristic; that is, the average gain loss in dB (see Figure 2) is constant attenuation for each equal increment of the control voltage (VCNTL) The divider is essentially a variable voltage divider consisting of a series input resistor (RS) and seven parallel FETs that are connected in parallel and controlled by sequentially activated limiting amplifiers (A1 to A7). vcntl is a valid difference between vcntlp and vcntlm. Each clipping amplifier can be understood as a dedicated voltage comparator with soft transfer characteristics and well-controlled output limit voltage. The reference voltages v1 to v7 are equally spaced in the 0V to 1.5V control voltage range. As the control voltage increases across the input range of each clipping amplifier, the amplifier output rises from a voltage where the FET is nearly off to a high voltage where the FET is fully on. As each FET approaches its on state and the control voltage continues to rise, the next shear amplifier/FET combination takes over the next part of the piecewise linear decay characteristic. Therefore, the low control voltage turns off most of the FETs, resulting in minimal signal attenuation. Likewise, a high control voltage turns on the FET, resulting in maximum signal attenuation. Therefore, the role of each FET is to reduce the shunt resistance of the voltage divider formed by the RS and the parallel FET network.
Additionally, for better phase noise performance in the VCA5807, a digitally controlled TGC mode is implemented. The attenuator can be controlled digitally instead of analog by the control voltage VCNTL. This mode can be set by register bit 59[7]. The transformer divider adopts fixed series resistance, and the FET adopts parallel resistance. Each FET can be turned on by connecting switches SW1-7. Opening each switch produces about 6 dB of attenuation. This can be controlled by register bits 59[6:4]. This digital control feature removes noise in the VCNTL circuit, ensuring better signal-to-noise ratio and phase noise for the TGC path.

The noise of the voltage-controlled attenuator is monotonically related to the attenuation coefficient. At higher attenuation, the input-referred noise is higher and vice versa. The noise from the attenuator is then amplified by the PGA and becomes the noise floor at the ADC input. In the high attenuation operating range of the attenuator, where VCNTL is high, the input noise of the attenuator may exceed the output noise of the LNA; then the attenuator becomes the dominant noise source for the next PGA stage and ADC. Therefore, the noise of the attenuator should be minimized compared to the LNA output noise. The attenuator of the VCA5807 is designed to achieve very low noise at high attenuation (low channel gain) and to achieve a better signal-to-noise ratio in the near field.

Low input noise is preferred in PGAs, and its noise contribution should not degrade the ADC's signal-to-noise ratio too much after the attenuator. At minimum attenuation (for small input signals), LNA noise dominates; at maximum attenuation (for large input signals), PGA and ADC noise dominate. Therefore, as long as the amplified signal can exceed the noise floor of the ADC, the 24dB gain of the PGA can achieve a better signal-to-noise ratio.
The PGA current clamp circuit (Register 51) can be enabled to improve the overload recovery performance of the VCA. If we measure the standard deviation of the output after overload, it is normally about 3.2 LSB for 0.5 volts VCNTL, i.e. the output settles in about 1 clock cycle after overload. With the current clamp disabled, the value is closer to 4 LSB, which means it takes longer before the output settles; however, with the current clamp enabled, the HD3 will degrade for pga output levels >2dbfs. For example, for a –2dbfs output level, hd3 drops about 3db. To maximize the output dynamic range, a clamp circuit is used, and the maximum PGA output level can exceed 2VPP (0 dbfs linear output range). Therefore, an ADC with good overload recovery should be selected.

The VCA5807 integrates an anti-aliasing filter in the form of a programmable low-pass filter (LPF) in the transimpedance amplifier. The low-pass filter is a differential, active, third-order filter with a Butterworth characteristic, with a typical 18dB roll-off per octave. Programmable through the serial interface, the -1db frequency angle can be set to one of 10MHz, 15MHz, 20MHz and 30MHz. Set the filter bandwidth for all channels at the same time.
In addition, an optional DC offset correction circuit is implemented. This correction circuit is similar to the circuit used in the LNA. It extracts the DC component of the PGA output and feeds it back to the PGA's complementary input for DC offset correction. The DC offset correction circuit also has a high-pass response with a cutoff frequency of 80kHz. If <80kHz operation is required, the DC offset correction circuit can be disabled via Register 0x33[4].
CW Beamformer CW Doppler is a key feature of mid to high end ultrasound systems. Compared to TGC mode, the CW path needs to deal with high dynamic range and tight phase noise performance. Due to the stringent requirements described above, CW beamforming is usually implemented in the analog domain. Various beamforming methods are being implemented in ultrasound systems, including passive delay lines, active mixers, and passive mixers. Among them, the passive mixer realizes the optimization of power and noise. It meets the requirements of continuous wave processing such as wide dynamic range, low phase noise, accurate gain, and phase matching.
A simplified CW path block diagram and an in-phase or quadrature (I/Q) channel block diagram are given below. Each CW channel includes a low-noise amplifier, a voltage-to-current converter, a switch-based mixer, a shared summing amplifier with low-pass filter, and clock circuitry. All blocks include well-matched in-phase and quadrature channels for good image frequency rejection and beamforming accuracy. The results show that the image suppression ratio of the I/Q channel is better than the -46dbc required by the ultrasound system.

LNA configuration
LNA input coupling and decoupling
The LNA closed-loop structure is internally compensated for maximum stability without the need for external compensation components. The LNA input bias is 2.4V and requires AC coupling. A typical input configuration is shown in Figure 84. CIN is the input AC coupling capacitor. CACT is part of the actively terminated feedback path. CACT is required for clamp function even when active termination is not used. Recommended values for CACT ≥ 1 microF and CIN ≥ 0.1 microF. A pair of clamping diodes are usually placed between the T/R switch and the LNA input. Depending on the amplitude of the echo from the sensor, a Schottky diode with an appropriate forward voltage drop (ie BAT754 /54 series, BAS40 series, MMBD7000 series or similar) can be considered.

LNA input configuration This configuration minimizes any loading of the signal source that might otherwise result in a frequency-dependent voltage divider. The closed loop design yields very low offset and offset drift. cBypass (≥0.015 μF) is used to set the high pass filter cutoff frequency and decouple the complementary input. Its cutoff frequency is inversely proportional to the cBypass value. As shown in Table 8, the high power factor cutoff frequency can be adjusted through Register 59[3:2]. Low frequency signals output by the T/R switch, such as slow-ringing signals, can be filtered out. Additionally, the high power factor minimizes system noise from DC-DC converters, pulse repetition frequency (PRF) triggers and frame clocks. The signal processing unit of most ultrasound systems consists of a digital high-pass filter or a band-pass filter (BPF) in an FPGA or ASIC. Further noise suppression can be implemented in these modules. Can be disabled if low frequency signal detection is required in some applications

Voltage Controlled Attenuator
The attenuator in the VCA5807 is controlled by a pair of differential control inputs (VCNTLM/P pins). The differential control voltage is between 0 volts and 1.5 volts. This control voltage changes the attenuation of the attenuator according to the linear (unit: dB) characteristic of the attenuator. Its maximum attenuation (minimum channel gain) occurs at VCNTLP VCNTLM=1.5 V, and the minimum attenuation (maximum channel gain) occurs at VCNTLP-VCNTLM=0. The typical gain range is 40dB and remains the same regardless of PGA settings.
When only single-ended VCNTL signals are available, use
The VCNTLM pin is grounded. As shown in the figure below, the TGC gain curve is inversely proportional to VCNTLP-VCNTLM.

low frequency support
The VCA5807's signal chain can handle signal frequencies below 100kHz, making the VCA5807 useful not only in medical ultrasound applications, but also in sonar applications. The PGA integrator must be turned off to enable low frequency support. Meanwhile, as shown in Figure 65, a large capacitor such as 1 microF can be used to set the LNA DC offset correction circuit for low corner frequency
CW Configuration Continuous Wave Summing Amplifier In order to simplify the design of the continuous wave system, a summing amplifier is implemented in the VCA5807, which sums the current output of the 8-channel mixer and converts it into a differential voltage output. The summing amplifier features low noise and low power consumption while maintaining the full dynamic range required for continuous wave operation.
The summing amplifier has 5 internal gain adjustment resistors that provide 32 different gain settings. System designers can easily adjust the CW path gain based on signal strength and sensor sensitivity. For any other gain value, the external resistor option is supported. The gain of the summing amplifier is determined by the ratio of the 500 Ω resistor after the LNA to the internal or external resistor network REXT/INT, so the matching between these resistors plays a more important role than the absolute resistor value. More than 1% matching is achieved on the chip. Due to process variations, the absolute tolerance of the resistors may be higher. Gain errors between I/Q channels or between multiple VCAs may increase if external resistors are used. It is recommended to use internal resistors to set the gain for better gain matching (across channels and multiple VCAs). This summing amplifier has a first-order LPF response to the external capacitor CEXT to remove high frequency components in the mixer, such as 2F0±FD.

Multiple VCA5807s are typically used in parallel to expand the channel count of successive beamformers. The CW outputs of these VCA5807S can be summed and filtered externally to obtain the desired gain and filter response. An AC coupling capacitor CAC is required to block the DC component of the continuous wave carrier signal. CAC can vary from 1uF to 10sμF, depending on the low frequency Doppler signal required for slow blood flow. Before 16/18-bit differential audio ADCs, the I/Q outputs of multiple VCA5807S can be summed with a low-noise external differential amplifier. Consider using ultra-low noise differential precision amplifier opa1632 and ths4130.

The combination of clock noise and CW path noise can degrade CW performance. The internal clock circuit is designed for continuous wave operation with good phase noise requirements. The phase noise of the VCA5807 CW path is better than 155dBc/Hz at 1KHz offset. Therefore, the phase noise of the mixer clock input needs to be better than 155dbc/hz.
In 16, 8, 4×_CW operating modes, 16, 8, 4×_CW clocks require a low phase noise clock (ie,
CLKP U 16X/CLKM U 16X pins) to maintain good CW phase noise performance. The 1×_CW clock (ie CLKP U1X/CLKM U1X pins) is only used to synchronize multiple VCA5807 chips, not for demodulation. Therefore, the phase noise of the 1_cw clock is not an issue. A continuous clock with a frequency of _cw or a single pulse with a width greater than 1/(n_cw) can be used.
On the other hand, in 1×_CW mode of operation, a low phase noise clock is required since both CLKP U16X/CLKM U16X and CLKP U1X/CLKM U1X pins are used for mixer demodulation. In general, high rev rate clocks have lower phase noise, so high amplitude and fast rev rate clocks are preferred in CW operation. In CMOS clock mode, a 5V CMOS clock can achieve the highest conversion rate.
Dividers can improve clock phase noise as long as the phase noise of the divider is lower than the target phase noise. The phase noise of a divided clock can be improved by about 20log10n db, where n is a division factor of 16, 8, or 4. If the target phase noise of the mixer low clock 1×_cw is 160dbc/hz at 1KHz non-carrier, then the clock phase noise of 16×_cw should be better than 160-20log1016=136dbc/hz. TI's jitter cleaner LMK048X/ CDCM7005 /CDCE72010 exceeds this requirement and can be used in the VCA5807. In 4x/1x mode, a high-quality input clock is expected to achieve the same performance due to smaller n. Therefore, 16X mode is the preferred mode because it reduces the phase noise requirements of the system clock design. In addition, the phase delay accuracy is specified by the internal clock divider and distribution circuit. In 16x operating mode, the CW operating range is limited to 8 MHz due to 16x CLK. The 16x clock has a maximum clock frequency of 128 MHz. In 8x, 4x and 1x modes, high CW signal frequencies up to 15MHz can be supported with less performance degradation, e.g. phase noise is 9dB lower at 15MHz than at 2MHz
As the number of channels in the system increases, the clock distribution becomes more complex. Because the load capacitance of the clock buffer increases by a factor of n, it is not recommended to use one clock driver output to drive multiple VCAs. Therefore, the fall and rise times of the clock signal are reduced. A typical clock arrangement for multiple VCA5807s is shown in Figure 95. Each clock buffered output drives one VCA5807 for best signal integrity and fastest slew rate, i.e. better phase noise performance. When clock phase noise is not an issue, Thai is. 1×_CW Clock In 32, 16, 8, 4×_CW operating modes, one clock driver output may excite more than one VCA5807S, but special consideration should be given in the design of such a clock distribution network. In a typical ultrasound system, all clocks are preferably generated from the same clock source, such as 16x_cw, 1x_cw clock, audio ADC clock, RF ADC clock, pulse repetition frequency signal, frame clock, etc. By doing this, disturbances caused by clock asynchrony are minimized.

CW Support Circuits As a general practice in CW circuit design, the in-phase and quadrature channels should be strictly symmetrical, with well-matched layouts and high-precision components.
In the system, additional high-pass wall filters (20Hz to 500Hz) and low-pass audio filters (10kHz to 100kHz) with multi-poles are usually required. Since CW Doppler signals range from 20Hz to 20kHz, noise in this range is critical. Therefore, low noise audio op amps are suitable for building active filters for CW post-processing, i.e. opa1632, opa2211, lme49990, lmh6629 or ths4130. More filter design techniques can be found on . TI's Active Filter Designer/docs/toolsw/folders/print/filterdesigner.html
The filtered audio CW I/Q signal is sampled by the audio ADC and processed by the DSP or PC. Although the frequency of CW signals is between 20 Hz and 20 kHz, higher sampling rate ADCs are still preferred for further extraction and signal-to-noise ratio enhancement. Due to the large dynamic range of continuous wave signals, high-resolution ADCs (≥16 bits) are required, such as ADS8413 (2MSPS/16it/92DBFS SNR) and ADS8472 (1MSPS/16bit/95DBFS SNR). In order to achieve the best I/Q matching, the ADCs of the in-phase and quadratic phase channels must be closely matched, not only in amplitude but also in phase. Additionally, the in-phase and quadrature ADC channels must be sampled simultaneously.
Power Management Power/Performance Optimization

Power Management Priorities Power management plays a critical role in extending battery life and ensuring long-term operation. The VCA5807 features fast and flexible power-down/power-up control to maximize battery life. The VCA5807 can be powered down/powered up via external pins or internal registers. The following table shows the circuit blocks and priorities that are affected when power management is invoked. In this device, all power-down controls are logically OR'ed to generate the final power-down of the different modules. Therefore, high-priority controls can override low-priority controls. The VCA5807 register settings remain unchanged when the VCA5807 is in partial power-down mode or full power-down mode.

Partial power-up/power-down mode is also known as fast power-up/power-down mode. In this mode, most amplifiers in the signal path are powered down, while the internal reference circuit remains active.
The partial power-down feature allows the VCA5807 to quickly wake up from a low-power state. This configuration ensures that the external capacitors discharge slowly, so as long as the charge on these capacitors is restored, minimal wake-up time is required. The VCA wake-up response is typically about 2 μs or 1% of the power-down duration, whichever is greater. The maximum wake-up time depends on the capacitors connected to INP and INM, as the wake-up time is the time required to charge the capacitors to the desired operating voltage. The wake-up time is 2.5ms for an inp of 0.1µF and an inm of 15nf. For larger capacitors, this time will be longer. Therefore, the VCA5807 wake-up time is more dependent on the VCA wake-up time. The power-off time is instantaneous, less than 1 microsecond.
This fast wake-up response is ideal for portable ultrasound applications where power savings is critical.
The pulse repetition rate of an ultrasound system can vary from 50 kHz to 500 Hz, while the imaging depth (i.e. the activation period of the receive path) can vary from 10 μs to hundreds of us. When the PRF of the system is low, the power saving effect is significant. In some cases, only the VCA is powered down while the ADC remains operational to ensure minimal impact on the FPGA.
In partial power-down mode, the VCA5807 typically dissipates only 12.5 mW/ch, an 80% power reduction compared to normal operation. This mode can be set using pin pdn_fast or register bit vca_partial_pdn.
Full Power Down Mode In order to achieve the lowest power consumption of 0.7mw/ch, the VCA5807 can be placed in full power down mode. This mode is controlled by register VCA_complete_PDN or PDN_global pin. In full power-down mode, all circuits including the reference circuit within the VCA5807 are powered down; capacitors connected to the VCA5807 are discharged. The wake-up time depends on how long it takes to charge these capacitors. The wake-up time depends on how long the VCA5807 is in shutdown mode.
INP is 0.1µF, INM is 15nF, and the wake-up time is close to 2.5ms.
CW Mode Power Saving Typically, in CW mode, only half of the channels in the system are active. Therefore, individual channel control through VCA_pdn_ch<7:0> can turn off unused channels and save power significantly. At the default register settings in CW mode, the voltage controlled attenuator PGA is still active. During the debug phase, both PW and CW paths can be run simultaneously. In actual operation, these modules need to be powered off manually.
Test Mode When direct probing of the VCA output is not feasible, the VCA5807 has a test mode in which the CH7 and CH8 PGA outputs can be brought to the CW pins. By monitoring these CW pins, the functionality of the VCA operation can be verified. The PGA outputs are connected to the virtual grounds of the summing amplifiers (CW_IP_Ampnm/p, CW_QP_Ampnm/p) through 5KΩ resistors. When the LPF capacitor CEXT is removed, the PGA output can be monitored at the summing amplifier output. Note that the signal at the output of the summing amplifier is attenuated by the 5KΩ resistor. The attenuation coefficient is rint/ext/5KΩ.
If the user wants to check the PGA output without removing the CExt, an alternative is to directly measure the PGA output at CW_IP_Ampnm/p and CW_QP_Ampnm/p when the CW summing amplifier is powered down.
Some registers are associated with this test mode. PGA test mode enabled: REG59[9]; buffer amplifier power down REG59[8]; buffer amplifier gain control REG54[4:0]. Depending on the configuration of the buffer amplifier, the registers can be set in different ways:
Configuration 1:
In this configuration, the test output can be monitored under cw_ampinp/m.
REG59[9]=1; test mode enabled
REG59[8]=0; Buffer Amplifier Power Down Configuration 2:
In this configuration, the test output can be monitored at cw_outp/m.
REG59[9]=1; test mode enabled
REG59[8]=1; the buffer amplifier is powered on
REG54[4:0]=10h; the internal feedback 2K resistor is enabled. Different values can also be used

Power, Ground, and Bypass Power and ground design plays an important role in mixed-signal system design. In most cases, the layout of the printed circuit board (PCB) should be sufficient to use the single ground plane of the VCA5807. It should be noted that this ground plane should be properly divided between the different parts within the system to minimize the interaction between the analog and digital circuits. In addition, opto-isolators or digital isolators (such as ISO7240 ) can completely separate the analog part from the digital part. Therefore, they prevent digital noise from contaminating the analog part.
All bypasses and power supplies for the VCA5807 should be referenced to their corresponding ground planes. All power pins should be bypassed with 0.1µF ceramic chip capacitors (size 0603 or smaller). To minimize lead and trace inductance, capacitors should be placed as close to the power pins as possible. If double-sided modules are allowed, it is best to place these capacitors directly below the modules. Additionally, larger bipolar decoupling capacitors (2.2µF to 10µF, effective at lower frequencies) are also available for the main supply pins. These components can be placed on a printed circuit board very close to the VCA5807 itself (<0.5 inches or 12.7 mm).
The VCA5807 has many reference supplies that need to be bypassed, such as CM-BYP, VHIGH, and VREF-IN. These pins should be bypassed by at least 1 µF; high value capacitors can be used to better suppress low frequency noise. For best results, choose a low-inductance ceramic chip capacitor (size 0402, >1 microF) and place it as close to the device pins as possible.
High-speed mixed-signal devices are sensitive to various noise couplings. A major source of noise is switching noise from serializers and output buffers/drivers. For the VCA5807, care has been taken to ensure that the interaction between the analog and digital power supplies within the device is kept to a minimum. The amount of noise coupled and transmitted by the digital and analog sections depends on the effective inductance of each power and ground connection. The smaller the effective inductance of the power and ground pins, the better the noise suppression. Therefore, use multiple pins to connect each power and ground device. By using proper planes and layer thicknesses, it is important to maintain low inductance characteristics throughout the PCB layout design process.
Proper ground and bypass layout, short lead lengths, and the use of ground and power planes are especially important for high-frequency designs. Achieving optimum performance with high-performance devices such as the VCA5807 requires careful attention to PCB layout to minimize the effects of board parasitics and optimize component placement. Multilayer printed circuit boards generally ensure the best results and allow for easy component placement.
Also, for CW clock paths, especially in systems with a high number of channels, proper delay matching should be considered. For example, if the clock delay is half of 16 times the clock period, there may be a phase error of 22.5°C. Therefore, the timing delay difference between channels contributes to the accuracy of the beamformer.
To avoid noise coupling through the power supply pins, it is recommended to keep sensitive input pins such as INM, INP, ACT pins always from the AVDD 3.3 V and AVDD 5V planes. For example, traces or vias connected to these pins should not pass through the AVDD 3.3 V and AVDD 5V planes.