DP83910A consists of five main logic blocks

1. The 10MHz transmit clock signal generated by the oscillator is the system timing

Second, the Manchester encoder accepts the encoded data from the NRZ data controller, and the difference between Manchester and anti-MITS to transmit the driver through the infinite interval of the transceiver with the difference

3. The Manchester decoder receives the data from the Manchester transceiver and converts it to NRZ data and clock pulses and sends it to the controller

Fourth, the crash transition indicates the presence of a valid 10MHz crash signal from the controller to the PLL

5. The loopback circuit asserted to route data from the Manchester encoder back to the PLL decoder

oscillator

The oscillator is controlled by a 20MHz parallel resonant crystal connected between X1 and X2 or by an external clock on X1. The 20MHz output of the oscillator is split and generated by 2 for control - the 10MHz transmit clock is not measurable The oscillator also provides an internal clock The signal is supplied to the encoding and decoding circuits. If the crystal is connected to the DP83910A it is recommended to use it as shown in the code, in the circuit diagram 1 can be used with the components used that meet the following crystal XT1 AT cut parallel resonant crystal series resistance s10x specified load capacitance 13pF 5 accuracy 0.005% (50ppm) C1 C2 load capacitance 27 pF in resistor R1 Figure 1 may be needed to minimize frequency drift due to changing supply voltage at VCC If R1 needs its value be sure to choose carefully -ED R1 reduces loop gain therefore , if R1 is made too large the loop gain will be greatly reduced and the crystal will not oscillate. If R1 is made by too small a normal change in VCC may cause the oscillation frequency to drift out of specification. The first rule of thumb is that the value of R1 should be equal to 5 times the dynamic resistance of the crystal for a 20MHz crystal, usually 10 times the dynamic resistance of the crystal To 30 times this range means that a reasonable value for R1 should be in the range of 50X -150X or not, including R1 should be based on the measured deviation of the crystal frequency Each circuit parameter is different according to the IEEE 802 standard for 3 whole oscillators The circuit (crytsal and amplifier) must be accurate to 0.01% when using the crystal X1 pin does not guarantee a TTL compatible logic output and should not be used to drive external standard logic.

Oscillator Module Operation

If the designer wishes to use a crystal clock oscillator 1 which provides the following should be used

1. TTL or CMOS output with a 0.01% frequency tolerance

2. 40%-60% duty cycle

3. t2 TTL load output driver

Function Description

The circuit is shown in Figure 2 (additional outputs can be driven as necessary if the oscillator must also drive other compositor fees) Using a clock oscillator it is still recommended that the designer connect the oscillator output to the X1 pin and tie the X2 pin to ground 3 3 Manchester Encoder and Differential Driver When the encoder starts to work, the transmit enable input (TXE) goes high and converts the clock and NRZ data to transmit data with TXE high for the duration related to the transmission and reception of Manchester data ( TXD) is encoded for the transmit driver pair (TXg) TXD must end of transmission on the rising edge of the valid transmit clock (TXC). When TXE goes low, the last transition is always positive. It occurs at the center of the bit cell if the last bit is 1 Or at the end of the bit cell, if the last bit is a zero differential transmit pair from the secondary's hetero-LATION transformer drives up to 50 meters of twisted pair?? AUI cable These outputs require two source-followers 270x pull-down resistor to ground The DP83910A allows both half-step and full-step to be Ethernet I and IEEE 802 3 compatible with the SEL pin low (for Ethernet I) transmitting a is relative to being transmitting b idle when SEL is high (for Ethernet I) IEEE 802 3) Transmit a and transmit b are equal, in idle state this provides zero differential voltage with transformer operation er coupled load

Manchester Decoder

The decoder includes a differential receiver and a PLL to separate the Manchester encoded data stream into the clock. The differential input of the NAL and NRZ data must be connected in series with two 39X resistors at the external end, if the standard 78X transceiver drop cable is used These resistors are optional for thin Ethernet net applications to prevent noise input from false triggering, the decoder squelch circuit rejects signals with levels less than b175mV once the input exceeds the squelch requirement Carrier Sense (CRS) Valid Received Data (RXD) and Received Clock (RXC) are generally valid at 6-bit times the DP83910A can tolerate a bit of jitter up to 18 ns of received data The decoder detects the end of a frame when no more midbit transitions are detected at a half-bit times After the last bit of carrier sense is de-asserted the receive clock remains active for a five-bit time, CRS goes low to ensure the timing of the received DP8390 NIC

translator collision

When the Ethernet transceiver (DP8392 CTI) detects colli-zion it will generate a 10 MHz signal to the differential collision input (CDg) of the DP83910A. When these inputs are deformed active the DP83910A converts the 10 MHz signal to an active high level for the controller. The controller uses this signal to back off its current transmit and resched-ule another bump to the differential input in the same way as the differential receive The input squelch circuit is also equally rejecting pulses less than level b175mV

Loopback function

When the loopback input (LBK) is set high, the DP83910A redirects its transmitted data back to its re-artifact path, this feature provides a convenient way to test both chip and system-level integrity transmit driver and receive input circuits are disabled loopback mode

block diagram: