The ZL2106 is a digital power conversion and management integrated circuit that combines an integrated synchronous buck DC/DC converter with key power management functions in a small package, resulting in a flexible, integrated solution.
The ZL2106 can provide an output voltage of 0.54V to 5.5V (with margin), and the input voltage is between 4.5V and 14V. Internal low RDS(ON) synchronous power MOSFETs enable the ZL2106 to deliver continuous loads up to 6A with high efficiency. Internal Schottky bootstrap diodes reduce discrete component count. The ZL2106 also supports phase expansion to reduce system input capacitance.
Power management functions, such as digital soft-start delay and ramping, sequencing, tracking and fringing, can be configured via simple pin strips or via the on-chip serial port. The ZL2106 communicates with the host controller using the PMBus protocol and uses a digital DC bus for interoperability between other Zilker lab equipment.
Features Integrated MOSFET switch • 6A continuous output current • ±1% output voltage accuracy • Parameter capture snapshot • I2C/SMBus interface, compatible with PMBus • Internal Non-Volatile Memory (NVM)
Applications • Telecom, Network, Storage Equipment • Test and Measurement Equipment • Industrial Control Equipment • 5V and 12V Distributed Power Systems Related Literature • AN1468 "ZL2106EVAL1Z Evaluation Board", USB Adapter Board, GUI Software • AN2010 "Digital DC Products Thermal and Layout Guidelines"
• AN2033 "Zilker Labs pmbus command set ddc products pmbus command set"
• AN2035 "Compensation with compzl"

Typical Application Circuit The application circuit below is a typical implementation of the ZL2106. For PMBus operation, it is recommended to connect the enable pin (en) to SGND.
Ferrite beads are optional for input noise rejection.
The pull-up resistors for the DDC bus will vary depending on the capacitive loading of the bus, including the number of devices connected. The 10 kΩ default value, assuming a maximum power of 100 pF per device, provides the necessary 1 microsecond pull-up rise time. See the Digital DC Bus section for details.
The IC/SMBus pull-up resistors will vary based on the capacitive loading of the bus, including the number of devices connected.
12V to 3.3V/6A Application Circuit (5ms SS Delay, 5ms SS Ramp)

ZL2106 Overview of Digital DC Architecture
The ZL2106 is an innovative mixed-signal power conversion and power management integrated circuit based on Zilker Labs patented digital DC technology that provides an integrated high-performance buck converter for point-of-load applications. The ZL2106 integrates all necessary PWM control circuits and low rds(on) synchronous power MOSFETs, providing a very small solution for supplying load currents up to 6A.
Its unique PWM loop utilizes an ideal combination of analog and digital modules, enabling precise control of the entire power conversion process without the need for software, resulting in a very flexible device that is also very easy to use. The extensive power management feature set is fully integrated and can be configured using simple pin connections. User configurations can be saved in internal non-volatile memory (NVM). Additionally, all functions can be configured and monitored via the smbus hardware interface using standard pmbus commands for maximum flexibility.
Once enabled, the ZL2106 is immediately ready to regulate power and perform power management tasks without programming. Advanced configuration options and real-time configuration changes are available via the I2C/SMBus interface if required, and multiple operating parameters can be continuously monitored with minimal interaction from the host controller. The integrated secondary regulation circuit enables single-supply operation from any external supply between 4.5 volts and 14 volts, eliminating the need for a secondary bias supply. The ZL2106 can also be configured to operate from a 3.3V or 5V backup supply when the main power rail is not present, allowing the user to configure and/or read diagnostic information from the device when the main power supply is interrupted or disabled.
The ZL2106 can be configured by simply connecting its pins according to the table provided in the following section. In addition, a comprehensive set of application notes is provided to help simplify the design process. An evaluation board is also available to help users become familiar with the device. The board can be evaluated as a standalone platform using the pin configuration settings. A Windows 8482 ; based graphical user interface is also provided, enabling complete configuration and monitoring functions through the I2c/SMBus interface using an available computer and the included USB cable.
Power Conversion Overview
The ZL2106 acts as a voltage mode, synchronous buck converter with optional constant frequency pulse width modulation (PWM) control scheme. The ZL2106 integrates dual low RDS(ON) synchronous MOSFETs to minimize circuit footprint.
Basic synchronous buck converter topology showing major powertrain components. This converter is also called a buck converter because the output voltage must always be lower than the input voltage.

ZL2106 Block Diagram Synchronous Buck Converter
The ZL2106 integrates two N-channel power MOSFETs; QH is the highest control MOSFET and QL is the lowest synchronous MOSFET. The amount of time qh occupies in the total switching cycle is called the duty cycle d, and is described by Equation 1:
During time d, QH is turned on and VIN–VOUT is applied to the inductor.
When QH is turned off (time 1-d), the current in the inductor must continue to flow from ground up through QL, during which time the current drops. Because the output capacitor exhibits low impedance at the switching frequency, the AC component of the inductor current is filtered out of the output voltage, so the load sees almost a DC voltage.
The maximum conversion ratio is shown in Figure 9. Typically, Buck converters are specified with a maximum duty cycle, effectively limiting the maximum output voltage achievable for a given input voltage and switching frequency. This duty cycle limit ensures that the low-side MOSFET is allowed to turn on for the minimum amount of time during each switching cycle, allowing the bootstrap capacitor to charge and providing sufficient gate drive voltage for the high-side MOSFET.

In general, the size of components l1 and cout and the overall efficiency of the circuit are inversely proportional to the switching frequency fsw. Therefore, the most efficient circuit can be achieved by switching the MOSFETs at the lowest possible frequency; however, this will result in the largest component size. Conversely, the smallest possible footprint can be achieved by switching at the fastest possible frequency, but this reduces efficiency. When determining the switching frequency for each application, each user should determine the best combination of size and efficiency.
The block diagram of ZL2106 is shown in Figure 11. In this circuit, the target output voltage is regulated by connecting the VSEN pin directly to the output regulation point. The VSEN signal is then compared to an internal reference voltage set by the user to the desired output voltage level. The error signal obtained by this comparison is converted into a digital value by an analog-to-digital (A/D) converter. The digital signal is also applied to an adjustable digital compensation filter, which is used to drive the appropriate PWM duty cycle of the internal MOSFET in a way that produces the desired output.
Power Management Overview
The ZL2106 integrates a series of configurable power management functions that can be easily implemented without additional components. In addition, the ZL2106 features circuit protection that continuously protects equipment and loads from damage caused by unexpected system failures. The ZL2106 continuously monitors input voltage, output voltage/current and internal temperature. A power good output signal is also included to enable the power-on reset function of the external processor.
All power management functions can be configured using pin configuration techniques or through the I2c/SMBus interface. Monitoring parameters can also be preconfigured to provide alerts for specific situations.
Multimode Pins To simplify circuit design, the ZL2106 features patented multimode pins that allow users to easily configure many aspects of the device without programming. Most power management functions can be configured using these pins. Multimode pins can respond to four different connections, as shown in Table 1. These pins are sampled when power is applied or when the pmbus restore command (see application note AN2033) is issued.
Strap Setup This is the easiest method as no additional components are required. Using this method, each pin can accept one of three possible states: low, on, or high. These pins can be connected to the V2P5 pin for a logic high setting since this pin provides a regulated voltage higher than 2V. Use a single pin to select one of three settings.

Resistor Setting This method allows a larger adjustable range when a finite value resistor (within the specified range) is connected between the multimode pin and SGND.
Using the standard 1% resistor values and using only every fourth E96 resistor value allows the device to reliably identify the resistor value connected to the pin while eliminating errors associated with resistor accuracy. Using one resistor provides up to 31 unique options.
IC/SMBUS Method 2
ZL2106 functions can be configured through the I2c/SMBus interface using standard PMBus commands. Additionally, any value configured using the pin strip or resistor setup method can also be reconfigured and/or verified via I2C/SMBUS. See application note AN2033 for more details.
smbus device address and vout_max are the only parameters that must be set by external pins. All other device parameters can be set via I2C/SMBus. The device address is set using the sa pin. Vout_max is determined to be 10% higher than the voltage set by the VSET pin.
Resistor pin strips are recommended for all available device parameters for a safe initial power-up prior to storing the configuration via I2C/SMBus. This can be accomplished, for example, by fixing the undervoltage lockout threshold (using the ss-pin) to a value greater than the expected input voltage, preventing the device from enabling until the configuration file is loaded.
Power Conversion Functional Description Internal Bias Regulator and Input Power Connections
The ZL2106 employs three internal low dropout (LDO) regulators to bias the internal circuitry, enabling it to operate from a single input supply. The internal bias regulators are as follows:
•VR: The VR LDO provides a regulated 7V bias power supply for the high-side MOSFET driver circuit. It is powered by the VDDS pin and provides bias current internally. A 4.7µF filter capacitor is required at the VR pin. The VDDS pin directly powers the low-side MOSFET driver circuit.
•VRA: The VRA LDO provides a regulated 5V bias supply for current sense circuits and other analog circuits. It is powered by the VDDS pin and provides bias current internally. A 4.7µF filter capacitor is required at the VRA pin.
Input Power Connections • V2P5: The V2P5 LDO provides a regulated 2.5 V bias power supply for the main controller circuit. It is powered by the VRA LDO and provides bias current internally. A 10µF filter capacitor is required on the V2P5 pin.
The VR and VRA pins should not be connected to any other pins when the input supply (VDDS) is above 7.5V. Only one filter capacitor can be connected to these pins. Due to the voltage drop associated with VR and VR bias regulators, the VDDS pin must be connected to these pins for designs operating below 7.5 volts. Connection required in all cases.
Note: The internal bias regulators, VR and VRA, are not outputs designed to power other circuits. Do not connect external loads to any of these pins. Only multimode pins can be connected to the V2P5 pin for logic high settings.
High side driver boost circuit The gate drive voltage of the high side MOSFET driver is generated by the floating bootstrap capacitor CB When the lower MOSFET (QL) is turned on, the sw node is pulled to ground and the capacitor is biased from the internal vr through the diode db Regulator charging. When ql is off and the upper MOSFET (qh) is on, the sw node is pulled to vddp and the voltage on the bootstrap capacitor is boosted to about 6.5 V above vddp to provide the necessary voltage to power the high side drivers. Internal Schottky diodes are used with CB to help maximize the high side drive supply voltage Output voltage selection The output voltage can be set to any voltage between 0.6V and 5.0V, provided the input voltage is higher than the desired output voltage, and sufficient to prevent the device from exceeding its maximum duty cycle specification. Using the pin-strap method, VOUT can be set to one of three standard voltages

starting program
The ZL2106 follows a specific internal startup procedure after powering up the VDD pins (VDDP and VDD). Table 3 describes the startup sequence.
If the device is to be synchronized to an external clock source, the clock frequency must be stable before asserting the en-pin. The device takes about 5ms to 10ms to check a specific value stored in its memory. If the user has stored values in memory, those values will be loaded. The device will then check the status of all multimode pins and load the values associated with the pin settings.
After this process, the device is ready to accept commands through the I2c/SMBus interface and the device is ready to be enabled. Once enabled, the device takes about 2 milliseconds to allow its output voltage to begin the ramping process. If the soft-start delay is less than 2ms (using the pmbus command), the device will default to a 2ms delay. If the configured delay time is greater than 2 ms, the device will wait the configured delay time before starting the ramp output.
After the delay period expires, the output will begin ramping toward the target voltage according to the preconfigured soft-start ramp time set using the SS pin. It is important to note that if the en-pin is connected to vddp or vdds, it will still take about 5 ms to 10 ms for the device before the output starts to ramp up as described in Table 3.
Soft-start delay and ramp time may be required to set the delay from when the enable signal is received until the output voltage begins to rise to the target value. Additionally, the designer may wish to set the time required for VOUT to ramp to its target value after the delay period expires. These features can be used as part of an overall inrush current management strategy or to control the speed at which a load IC turns on. The ZL2106 provides system designers with several options for precise and independent control of delay and ramp time periods.

The soft-start delay period begins when the en-pin is asserted in Table 6. Delay and ramp configuration, which ends when the delay time expires. The soft-start delay time is set using the SS pin. Precise ramp-delay timing mode reduces delay time variation and is available when the appropriate bits in the misc-config register are set. Please refer to application note AN2033 for details.
A soft-start ramp timer enables precise control of the ramp to the nominal VOUT value, which begins once the delay period has elapsed. Climbing is guaranteed to be monotonic, and its slope can be precisely set using SS pins. Using the pin-band method, the soft-start delay and ramp time can be set to one of three standard values according to Table 5. Soft-start delay and ramp settings If the desired soft-start delay and ramp time are not one of the values listed in Table 5, The time can then be set to a custom value by connecting a resistor from the SS pin to SGND using the appropriate resistor values from Table 6. The value of this resistor is measured at startup or recovery and will not change if the resistance changes after the ZL2106 is powered up.
Stainless steel pin resistor connections Soft-start delay and ramp time can also be set to custom values via the I2C/SMBus interface. When the SS delay time is set to 0ms, the device will start to climb after the internal circuit is initialized (about 2ms). When the soft-start ramp period is set to 0 ms, the output will ramp up quickly as the output load capacitance and loop settings allow. It is generally recommended to set the soft-start ramp to a value greater than 500 microseconds to prevent unexpected failures due to excessive inrush currents.
Power Good (PG)
The ZL2106 provides a Power Good (PG) signal indicating that the output voltage is within the specified tolerance of its target level and that no fault conditions exist. By default, the PG pin will be asserted if the output is within +15%/-10% of the target voltage. These limits can be changed via the I2c/SMBus interface. See application note AN2033 for details.
The pg latency period is the time from when all the conditions for asserting the pg are met until the pg pin is actually asserted. This function is typically used in place of an external reset controller to signal the target voltage of the power supply before enabling any powered circuits. By default, the ZL2106 PG delay is set to 1ms, which can be changed using the I2c/SMBus interface described in AN2033.
Switching Frequency and Phase Locked Loop
The ZL2106 integrates an internal phase-locked loop (PLL) to clock the internal circuits. The PLL can be driven by an external clock source connected to the sync pin. When using the internal oscillator, the sync pin can be configured as a clock source for other Zilker Labs devices.
A sync pin is a unique pin that can perform multiple functions depending on how it is configured. The cfg pin is used to select the operating mode of the sync pin Configuration A:
When the sync pin is configured as an output (cfg pin is held high), the device will run from its internal oscillator and drive the resulting internal oscillator signal (preset at 400kHz) onto the sync pin so that Other devices can sync with it. In this mode, the sync pins are not checked for incoming clock signals.
Configuration B:
When the sync pin is configured as an input (CFG pin connected low), the device will automatically check for an external clock signal on the sync pin each time the EN pin is asserted. The internal oscillator will then be synchronized to the rising edge of the external clock. The incoming clock signal must be in the range of 200kHz to 1MHz with a minimum duty cycle and must be stable when the en pin is asserted. The external clock signal must also exhibit the necessary performance requirements (see the "Electrical Specifications" table starting on page 6).
In the event of loss of external clock signal, the output voltage may show transient over/undershoot. If this happens, the ZL2106 will automatically switch to its internal oscillator and switch at a frequency close to the previous input frequency.
Configuration C: Sync Auto Detect When the sync pin is configured in auto detect mode (the cfg pin is left open), the device will automatically check that the enabled sync pin is asserted. If a valid clock signal is present,

If no clock signal is input, the ZL2106 will configure the switching frequency according to the state of the sync pins listed in Table 8. In this mode, the ZL2106 only reads the sync pin connections during startup. Changes to the sync pin connections will not affect the FSW until the power supply (VDD) is cycled off and on again.

Inductor selection The selection process for the output inductance must include several trade-offs. High inductance values will result in low ripple current (IOPP), which will reduce output capacitance and produce low output ripple voltage, but may also affect output transient load performance. Therefore, a balance must be struck between output ripple and optimum load transient performance. A good starting point is to choose an output inductor ripple equal to the expected load transient step magnitude (iostep):
Friction stir welding × I eyepiece lung plethysmogram The average inductor current is equal to the maximum output current. The peak inductor current (ILPK) is calculated using Equation 4, where IOUT is the maximum output current:
Choose an inductor with a peak current rating higher than the peak current calculated in Equation 4 for the average DC current.
During overcurrent or short circuit conditions, the inductor current may be greater than 2 times the normal maximum rated output current. In this case, an inductor that still provides some inductance needs to be used to protect the load and internal MOSFETs from damaging currents.
Once an inductor has been selected, the DCR and core losses of the inductor can be calculated. Use the DCR specified in the inductor manufacturer's data sheet.
where iout is the maximum output current. Next, calculate the core loss for the selected inductor. Since this calculation is specific to each inductor and manufacturer, please refer to the selected inductor data sheet. Add core losses and DCR losses and compare the total losses to the maximum power dissipation recommendations in the inductor datasheet.
Output Capacitor Selection Several tradeoffs must also be considered when selecting an output capacitor. During transient load steps (Vosag) and low output voltage ripple (Vorip), output deviation of low ESR values is required. However, low ESR capacitors, such as semi-stable (X5R and X7R) dielectric ceramic capacitors, also have relatively low capacitance values. Many designs can use both high capacitance devices and low ESR devices.
For high ripple currents, low capacitor values result in a large amount of output voltage ripple. Also, during high transient load steps, when the inductor current rises or falls to the new steady-state output current value, a relatively large capacitor is required to reduce the output voltage deviation.
Use these values for initial capacitor selection, using a single capacitor or multiple capacitors in parallel.
After selecting the capacitor, the resulting output voltage ripple can be calculated using Equation 9:
Since each part of this equation is less than or equal to half the allowable output ripple voltage, Vorip should be less than the desired maximum output ripple.
Input Capacitors Dedicated input capacitors are strongly recommended at any load design point, even if the supply is powered from an off-line supply by a heavily filtered 5-volt or 12-volt "bulk" supply. This is due to the high rms ripple current produced by the Buck converter topology. This ripple (Icinrms) can be determined by Equation 10:
Without capacitive filtering near the power circuit, current will flow through the power bus and return plane, coupling noise into other system circuits. The input capacitor should be rated at 1.2 times the ripple current calculated in Equation 10 to avoid overheating the capacitor due to excessive ripple current, resulting in premature failure. Ceramic capacitors with X7R or X5R dielectric are recommended, with low ESR and a maximum expected input voltage of 1.1X.
Bootstrap Capacitor Selection The high-side driver boost circuit utilizes an internal Schottky diode (DB) and an external bootstrap capacitor (CB) to provide adequate gate drive for the high-side MOSFET driver. The circuit breaker should be a 47nF ceramic type with a voltage rating of at least 10V.
CSelect V2P5
This capacitor is used to stabilize the 2.5V internal power supply and provide noise filtering. Should be between 4.7µF and 10µF, should use a semi-stable X5R or X7R dielectric ceramic, low ESR (less than 10MΩ), and should be rated at 4V or higher.
C select VR This capacitor is used to stabilize the 7V reference supply and provide noise filtering. It should be between 4.7µF and 10µF, a semi-stable X5R or X7R dielectric ceramic capacitor should be used, have low ESR (less than 10MΩ), and should have a 10V rating or higher. Because the bootstrap supply current is drawn from this capacitor, the magnitude of CVR should be at least 10 times the value of CB so that the discharged CB does not cause an excessive drop in voltage across it during the CB charge pulse.
CSelect VRA
This capacitor is used for stabilization and to provide noise filtering for the analog 5V reference supply. Should be between 2.2µF and 10µF, semi-stable X5R or X7R dielectric ceramic capacitors should be used, low ESR (less than 10MΩ), and should be rated at 6.3V or higher.
In typical applications, the high efficiency of the ZL2106 will limit the power dissipation inside the package. However, in applications requiring high ambient operating temperatures, the user must perform some thermal analysis to ensure that the maximum junction temperature of the ZL2106 is not exceeded.
The ZL2106 has a maximum junction temperature limit of +125°C, and an internal overtemperature limit circuit will force the device to shut down when the junction temperature exceeds this threshold. In order to calculate the maximum junction temperature, the user must first calculate the power dissipated inside the IC (PQ),
The ZL2106 employs a patented "lossless" current sensing method through an internal low-side MOSFET that is unaffected by RDS(on) changes, including temperature. The default value of gain (which does not represent the rds(on) value) and the offset of the internal current sensing circuit can be modified by the Output Calibrate Gain and Output Calibrate Offset commands.
The design should include a current limiting mechanism to protect the power supply from damage and prevent excessive current from the input power supply if the output is shorted to ground or an overload condition is applied to the output. Current limit is achieved by inducing current through the circuit for a fraction of the duty cycle. By default, the current limit threshold is set to 9A. The current limit threshold can be set to a custom value via the I2c/SMBus interface.
In addition, the ZL2106 provides power supply designers with a choice of fault response under overcurrent or current conditions. The user can select the number of violations allowed before declaring a fault, the blanking time, and the action to take when a fault is detected. Blank time represents the time when no current measurement is made. This is to avoid taking readings after the current loading step (less accuracy due to possible ringing).
loop compensation
ZL2106, as a voltage-type synchronous step-down controller, adopts a fixed-frequency pulse width modulation scheme. Although the ZL2106 uses a digital control loop, it works very similarly to a traditional analog PWM controller. Figure 17 is a simplified block diagram of the ZL2106 control loop, which differs from the analog control loop only by the constants in the PWM and compensation blocks. As in the case of the analog controller, the compensation block compares the output voltage to the desired reference voltage and adds a compensation zero to keep the loop stable. The resulting integrated error signal is used to drive the PWM logic, converting the error signal to a duty cycle to drive the internal

In the ZL2106, after the user has calculated the desired setting, the compensation zero is set by configuring the FC pins or through the I2C/SMBus interface. This approach eliminates errors due to component tolerances due to the use of external resistors and capacitors required by traditional analog controllers.
The loop compensation factor can also be set via the I2c/SMBus interface. Please refer to application note AN2033 for details. For more technical details on setting up loop compensation, see application note AN2035.
Driver Dead Time Control
The ZL2106 utilizes a predetermined fixed dead time applied between the gate drive signals of the top and bottom MOSFETs.
In a synchronous buck converter, the operation of the MOSFET driver circuit must ensure that the top and bottom MOSFETs are not conducting at the same time. This is because if both MOSFETs are turned on simultaneously for more than a few nanoseconds, there can be damaging current flow in the circuit. Conversely, prolonged periods where both MOSFETs are off reduces overall circuit efficiency by allowing current to flow in their parasitic body diodes.
Therefore, dead-time is minimized to provide the best efficiency without compromising system reliability. The ZL2106 optimizes the dead time of the integrated MOSFET to maximize efficiency.
Power Management Functional Description Input Undervoltage Lockout Input undervoltage lockout (uvlo) prevents the ZL2106 from operating when the input falls below a preset threshold, indicating that the input power is outside its specified range. According to Table 6, the UVLO threshold (vuvlo) can be set to 4.5 V or 10.8 V using the SS pin.
The UVLO voltage can also be set to any value between 2.85V and 16V via the I2C/smbus interface.
In the event of an input undervoltage fault, the device can respond in the following ways: 1. Continue to operate without interruption.
2. Continue to run for the given delay time and stop if the fault still exists. The device will remain off until instructed to restart.
3. Immediately shut down until the fault is cleared. The user can choose a specific number of retries.
The default response to uvlo failure is to shut down the device immediately. See application note AN2033 for details on how to configure UVLO thresholds or select specific UVLO fault response options via the i2c/smbus interface.
Output overvoltage protection
The ZL2106 provides an internal output overvoltage protection circuit that can be used to protect sensitive load circuits from voltages above their specified limits. A hardware comparator is used to compare the actual output voltage (at the VSEN pin) with a threshold (default setting) set 15% above the target output voltage. If the VSEN voltage exceeds this threshold, the PG pin will be de-asserted and the device can then respond in a number of ways:
1. Immediately shut down until the fault is cleared. The user can choose a specific number of retries.
2. Turn off the high-side MOSFET and turn on the low-side MOSFET. The low-side MOSFET remains on until the device attempts to restart.
The default response to an overvoltage fault is an immediate shutdown. For continuous overvoltage protection when operating from an external clock, the only allowed response is immediate shutdown. See application note AN2033 for details on how to select specific overvoltage fault response options via I2c/SMBus.
Output Pre-Bias Protection An output pre-bias condition exists when an externally applied voltage is present on the output of a power supply before the power supply's control IC is enabled. In some applications, if a pre-bias condition exists at the output, the converter is not allowed to sink current during startup. The ZL2106 provides pre-bias protection by sampling the output voltage before starting the output ramp.
If, after the preconfigured delay period, there is a pre-bias lower than the target voltage, the target voltage will be set to match the existing pre-bias and both drivers will be enabled. The output voltage is then ramped to the final regulated value at the ramp rate set by the SS pin.
The actual time it takes for the output to transition from the pre-bias to the target voltage will vary based on the pre-bias, but the total time required from the end of the delay period until the output reaches the target value will match the pre-configured transition time if at the pre-configured delay After the period, there is a pre-bias higher than the target voltage, the target voltage is set to match the existing pre-bias, and both drivers are enabled with a PWM duty cycle that ideally creates the pre-bias.
Once the pre-configured soft-start ramp period has elapsed, the PG pin will be asserted (assuming the pre-bias voltage is not higher than the overvoltage limit). The PWM will then adjust its duty cycle to match the original target voltage, and the output will drop to the preconfigured output voltage.

If there is a pre-bias above the overvoltage limit, the device will not initiate a turn-on sequence and an overvoltage fault condition will be declared. In this case, the device will respond according to the selected output overvoltage fault response method.
Output overcurrent protection
The ZL2106 can protect the power supply from damage if the output is shorted to ground or an overload condition is applied to the output. Once the current limit threshold is selected, the user can determine the desired course of action based on the fault condition. The following overcurrent protection response options are available:
1. Initiate a shutdown and attempt an infinite restart with a preset delay period between attempts.
2. Initiate a shutdown and attempt a preset number of restarts within a preset delay time between attempts.
3. Continue to run for the given delay time and stop if the fault still exists.
4. Continue through the fault (this may cause permanent damage to the power supply).
5. Immediately shut down.
6. The default response to an overcurrent fault is to shut down the device immediately. See application note AN2033 for details on how to select specific overcurrent fault response options via I2c/SMBus.
Thermal overload protection
The ZL2106 includes an on-chip thermal sensor that continuously measures the internal temperature of the mold and shuts down the device when the temperature exceeds preset limits. The factory default temperature limit is set to +125°C, but the user can set the limit to another value if desired. See application note AN2033 for details. Note that setting higher thermal limits via the I2C/SMBus interface may result in permanent damage to the device. Once the device is disabled due to an internal temperature fault, the user can choose one of several fault response options:
1. Initiate a shutdown and attempt an infinite restart with a preset delay period between attempts.
2. Initiate a shutdown and attempt a preset number of restarts within a preset delay time between attempts.
3. Continue to run for the given delay time and stop if the fault still exists.
4. Continue through the fault (this may cause permanent damage to the power supply).
5. Immediately shut down.
If the user has configured the device to restart, the device will wait a preset delay time (if configured to do so) and then check the device temperature. If the temperature falls below a threshold of approximately +15°C below the selected temperature fault limit, the device will attempt to restart. If the temperature still exceeds the fault limit, the device will wait the preset delay time and try again.
The default response to a temperature fault is to shut down the device immediately. See application note AN2033 for details on how to select specific temperature fault response options via I2c/SMBus.
Voltage tracking high-performance systems place strict requirements on the turn-on sequence of the supply voltage. This is especially true when powering FPGAs, ASICs, and other advanced processor devices that require multiple supply voltages to power a single chip. In most cases, the I/O interface operates at a higher voltage than the core, so according to the manufacturer's specifications, the core supply voltage must not exceed the I/O supply voltage. Voltage tracking protects these sensitive ICs by limiting the differential voltage between multiple power supplies during power-up and power-down. The ZL2106 integrates a lossless tracking scheme that allows its output to track the voltage applied on the VTRK pin, requiring no additional components. Figure 19 shows a basic I2c/SMBus trace configuration. For more information on configuring trace mode using the pmbus command, see application note AN2033.
An example of a basic pin tape tracking configuration. The vtrk pin is an analog input, and when tracking mode is enabled, the voltage applied to the vtrk pin is used as a reference for the output voltage of the device. ZL2106 provides two tracking modes: Coincidence and Ratio measurement Basic I2C tracking configuration
1. coincide. This mode configures the ZL2106 so that its output voltage is the same as applied to
VRTK pin. There are two options available for this mode;
A. 100% VOUT LTD track.
b. 100% VTRK Limited Orbit.
coincidence tracking
2. This mode of proportionality configures the ZL2106 to ramp its output voltage as a percentage of the voltage applied to the VTRK pin. The default setting is 50%, but external resistors can be used to configure different tracking ratios.
A. 50% VOUT CO. TRAIN. The member track tracks the reference track and stops when the member reaches 50% of the target voltage, b. 50% VTRK Ltd's track. The member rail tracks the reference at the instantaneous voltage value applied to the vtrk pin until the member rail reaches 50% of the reference rail voltage, or if the member is configured to be less than 50% of the reference rail voltage, the member will achieve its configuration target tracking overview When the ZL2106 is configured in voltage tracking mode, the voltage applied on the VTRK pin is used as the reference for the output regulation of the member device. The soft-start value (rise/fall time) is used to calculate the loop gain used during the on/off ramp, so the minimum rise/fall time is limited to 5 ms for accuracy. Tracking accuracy can be improved by adding rise and fall times beyond 5ms.
Tracking group In a tracking group, the device configured with the highest voltage in the group is defined as the reference device. Devices that track references are called member devices. The reference unit will control the ramp delay and ramp rate for all tracking units and is not in tracking mode.
The reference device is configured to the highest output voltage of the group, and the output voltages of all other devices are designed to track without exceeding the output voltage of the reference device.
This delay allows member devices to prepare their control loops for tracing after the assertion is enabled.
Member device off delay has been redefined to describe how long the vtrk pin will follow the reference voltage after de-assertion is enabled. If the reference output voltage does not reach zero volts, the delay setting sets the timeout for the member output voltage to off.
The component arrangement must have a minimum closing delay as shown in Equation 14.
For tracking groups, it is assumed that all enable pins are connected together and driven by a logic source or PMBUS broadcast enable.
The ZL2106 provides an easy way to change its output above or below its rated voltage setting to determine if the load device can operate within its specified supply voltage range. The mgn command is set by driving the mgn pin or through the i2c/smbus interface. The mgn pin is a tertiary input that is continuously monitored and can be directly driven by processor I/O pins or other logic-level outputs.
When the mgn command is set high, the output of the ZL2106 will be forced above its nominal set point, and when the mgn command is set low (low), the output will be forced below its nominal set point. A default margin limit of Vnom±5% is preloaded at the factory, but the margin limit can be modified to Vnom+10% or 0V via the I2c/Smbus interface, where Vnom is set by the rated output voltage determined by the VSET pin point. ZL2106-01 allows a 150% profit limit.

Digital DC Bus The Digital DC Communication (DDC) bus is used for communication between Zilker Labs digital DC devices. This dedicated bus provides functions such as sequencing and fault expansion for communication channels between devices. The DDC pins on all digital DC devices in the application should be connected together. A pull-up resistor is required on the DDC bus to ensure that the rise time is as shown in Equation 15:
Rise time = rpu • Cloaca ≈ 1 μs (Equation 15)
Where rpu is the DDC bus pull-up resistor, and cloud is the bus load. The pull-up resistor can be connected to VRA or an external 3.3V or 5V supply as long as this voltage is present before or during device power-up. As a rule of thumb, each device connected to the DDC bus will generate about 10pF of capacitive load, and about 2pF per inch of FR4 PCB trace. An ideal design would use a central pull-up resistor well matched to the total load capacitance. In power module applications, the user should consider whether to place the pull-up resistors on the module or on the PCB of the final application.
The minimum pull-up resistor should be limited to a value that allows any device to assert the bus to a voltage that will ensure a logic 0 (usually 0.8V at the device monitoring point), given the pull-up voltage (if connected to VRA, 5V) and the pull-down current capability of the ZL2106 (usually 4MA).

Phase Stretching When multiple load converters share a DC input supply, the clock phase offset of each device needs to be adjusted so that not all devices start switching at the same time. Setting each converter to begin its switching cycle at a different point in time can significantly reduce input capacitance requirements and efficiency losses. Since the peak current drawn from the input power is effectively spread out over a period of time, the peak current drawn at any given moment is reduced and the power loss proportional to IRMS2 is significantly reduced.
To achieve phase spreading, all converters must be synchronized to the same switching clock. The cfg pins are used to set the synchronization pin configuration for each device described in "Switching Frequency and PLL" on page 15.
Selecting the phase offset of the device is done by selecting the device address according to the following formula:
Phase offset = device address x 45°
E.g:
• When the device address is 0x00 or 0x20, the phase offset is not configured.
• A device address of 0x01 or 0x21 will configure a 45° phase offset • A device address of 0x02 or 0x22 will configure a 90° phase offset The phase offset for each device can also be set via the I2c/SMBus interface in 22.5° increments Any value between 0° and 360 °.
Output Sequence A group of Zilker lab devices can be configured to power up in a predetermined sequence. This feature is especially useful when powering advanced processors, FPGAs, and ASICs, which require one supply to reach its operating voltage before the other to avoid latch-up. Multi-device sequencing is possible by configuring each device via the i2c/smbus interface or using Zilker Labs patented autonomous sequencing mode.
Autonomous sequencing mode configures sequencing by using events transmitted between devices on the DDC bus.
Sort order is determined using each device's smbus address. With autonomous ordering mode (configured with cfg pins), devices must be assigned consecutive smbus addresses without missing addresses in the chain. This mode will also limit each device to have a phase offset based on the smbus address described in the "Phase Extension" section on page 24.

Monitoring via IC/SMBus2
The system controller can monitor various ZL2106 system parameters through the I2C/SMBus interface. The device can monitor fault conditions by monitoring the salrt pin, which is pulled low when any number of preconfigured fault conditions occur.
The device can also continuously monitor any number of power conversion parameters, including input voltage, output voltage, output current, internal junction temperature, switching frequency, and duty cycle.
The PMBus host should respond to salrt as follows:
1. The ZL device pulls the Salrt low.
2. The PMBus host detects that the salrt is now low and performs a transfer using the alert response address to find which zl device is pulling the salrt low.
3. The PMBus host talks to the zl device that pulls the salrt low. The action performed by the host is determined by the system designer.
If more than one device fails, salrt will still be low after the above steps, and the alarm response address needs to be repeatedly transmitted until all failures are cleared. For details on how to monitor specific parameters via the I2c/SMBus interface, see application note AN2033.
Snapshot™ parameter capture
The ZL2106 provides a special feature that allows the user to capture parametric data after normal operation or failure. The snapshot feature is enabled by setting bit 1 of misc-config to 1.
In addition to the supported parameters, the snapshot function allows the user to read parameters via the block read transfer via smbus. This can be done during normal operation, with the caveat that reading 22 bytes will take a while on the smbus.
Snapshot control commands allow the user to store snapshot parameters to flash in response to a pending failure, and to read the stored data from flash after a failure. Usage of this command. If the response to a specific fault is off, then an automatic post-fault write to flash is triggered when any of the fault threshold levels are exceeded (if the device is configured to retry flash writes under specific fault conditions, writes to flash are not allowed).
It should also be noted that the device's VDD voltage must be maintained while the device is writing data to flash; this process takes between 700 microseconds and 1400 microseconds depending on whether the data is set up for block writes. During this process, if the device's VDD supply drops below 3.0V, undesirable results may occur.

Follow the command (read data from RAM via smbus) to extract the last snapshot parameters stored during the failure.
Non-volatile memory and device security features
ZL2106 has internal non-volatile memory to store user configuration. Integrated security measures ensure that users can only restore the device to a level that they can use. Learn more about how the device loads stored values from memory during startup.
During initialization, the ZL2106 checks the stored values contained in its memory. The ZL2106 provides two internal memory storage units that the user can access via:
1. Default Storage: Power module manufacturers may wish to protect the module from damage by preventing users from modifying certain values related to the physical structure of the module. In this case, the module manufacturer will use the default storage and allow the user to restore the device to its default settings, but will restrict the user from restoring the device to factory settings.
2. User Storage: Device manufacturers may want to provide the ability to modify certain power settings while still protecting the device from modifying values that could lead to system-level failures. Device manufacturers will use user stores to achieve this.