The DAC8830 and DAC8831 are single-channel, 16-bit, serial input, voltage output digital-to-analog converters (DACs) that operate from a single 3V to 5V supply. These converters provide excellent linearity (1LSBINL), low glitch, low noise and fast settling (1.0μS1/2LSB full-scale output) over a specified temperature range of -40°C to +85°C. The output is buffered, thereby reducing power consumption and errors introduced by the buffer. These parts feature a standard high-speed (up to 50 MHz), 3V or 5V SPI serial interface to communicate with a DSP or microprocessor. The DAC8830 output is 0V to VREF. However, the DAC8831 provides bipolar outputs (±VREF) when working with external buffers. The DAC8830 and DAC8831 are reset to power after zero code. For best performance, a set of Kelvin connections to an external reference and analog ground are set at the DAC8831 input. The DAC8830 is packaged in SO-8, and the DAC8831 is packaged in SO-14. Both have industry standard pins. The DAC8831 is also available in a QFN-14 package.

The DAC structure of the digital to analog section contains two matched DAC sections and is segmented for both devices. The following diagram is shown in the simplified circuit diagram. The decoding of the resulting 4-bit 16-bit data word is used to drive 15 switches, E1 to E15. Each switch connects 15 matched resistors to either AGND or V1REF. The remaining 12-bit data word drivers switch S0 to S11 of the 12-bit voltage mode R-2R ladder network.

The output range at the output of the DAC is VOUT=(VREF×Code)/65536. Where CODE is the decimal data word loaded into the DAC latch.

Power-On Reset Both devices have a power-on reset feature to ensure that the output is in a known state at power-up. In the DAC8830 and DAC8831, upon power-up, the DAC latch and input register contain all 0s until new data is loaded from the input serial shift register. Therefore, after power-up, the output from this pin V OUT of the DAC8830 is 0V. The DAC8831 is output from pin V OUT in 0V unipolar mode and -VREF in bipolar mode. However, the serial registers of the DAC8830 and DAC8831 are not cleared on power-up, so their contents are undefined. When data is initially loaded into the device, 16 or more bits should be loaded to prevent erroneous data from appearing on the output. If more than 16 bits are loaded, the last 16 remain; if less than 16 bits are loaded, the bits will continue from the previous word. If the device must be interfaced with data less than 16 bits in length, the data should be padded with 0 bits.

The serial interface digital interface is compatible with SPI, QSPI™, MICROWIRE™ and TIDSP standard 3-wire connections and operates at speeds up to 50M bits/sec. The data transfer is through the CS frame, the chip select signal. The DAC works as a bus slave. The bus master generates the synchronization clock SCLK and initiates the transfer. When CS is high, the DAC is not accessed, and the clock SCLK and serial input data SDI are ignored. The bus master accesses the DAC by driving pin CS low. Immediately following a high-to-low CS transition, pin SDI serial input data is shifted out of the bus master synchronously on the falling edge of SCLK and latched into the shift register on the rising edge of SCLK, MSB first. A low-to-high burst transition transfers the contents of the input shift register to the input register. All data registers are 16 bits. This requires 16 clocks of SCLK to transfer a data word to the section. To complete the entire data word, CS must go high after 16 SCLK clock inputs. If the low state of CS is applied for more than 16 SCLKs, the last 16 bits are transferred to the input register on the rising edge of CS. However, if CS is not kept low for the entire 16 SCLK cycles, the data is corrupted. In this case, reload the DAC with a new 16-bit word. In the DAC8830, the contents of the input register are transferred to the DAC latch immediately after the input register is loaded, and the DAC output is updated at the same time. The DAC8831 has an LDAC pin that allows the DAC latch to go high after CS is asynchronously updated by bringing LDAC low. In this case, LDAC must remain high while CS is low. If LDAC is permanently tied low, the DAC latch is updated immediately after being loaded into the input register (caused by a low-to-high transition of CS).

DAC8830 block diagram

DAC8831 block diagram