Features Operating Input Voltage 10 V to 40 V Programmable Fixed Frequency up to
100 kHz to 1 MHz Voltage Mode Controller Internal Gate Drive Output for High Side and Synchronous N-Channel MOSFETs 16-pin PowerPad Package (JC=2c/w) Thermal Shutdown External Synchronous Programmable Short Circuit Protection Programmable Closed-Loop Soft-Start Application
DDR Tracking Regulator Power Module Network Equipment Industrial Server Simplified Application Diagram Illustration
The TPS40052 is part of a family of high voltage, wide input, synchronous buck converters. The TPS40052 offers design flexibility with multiple user-programmable features, including soft-start, operating frequency, high-side current limit, and loop compensation.

The TPS40052 can also be synchronized with an external power supply. It combines MOSFET gate drivers for external n-channel high-side and synchronous rectifier (SR) MOSFETs. The gate drive logic incorporates anti-cross-conduction circuitry to prevent simultaneous high-side and synchronous rectifier conduction.

Externally programmable short-circuit protection provides pulses with pulsed current limit, as well as hiccup mode operation for prolonged overloads using an internal fault counter.

The TPS40052 allows the user to optimize the PWM controller for a specific application.
The TPS40052 is the controller of choice for synchronous buck designs where the output needs to track another voltage. It has two-quadrant operation and can source or sink output current, providing the best transient response.
Switch Node Resistance and Diode When both the upper and lower MOSFETs are off, the switch node of the converter will be negative in the dead time. The magnitude of this negative voltage depends on the lower MOSFET body diode and the output current flowing during this dead time. This negative voltage can affect the operation of the controller, especially at low input voltages.
Therefore, as shown in Figure 10, a resistor (3.3 ohms to 4.7 ohms) and a Schottky diode must be placed between the lower MOSFET drain and the controller's contact pin 12 (sw). Schottky diodes must be voltage rated to accommodate the input voltage and ringing on the converter switch node. 30 Volt Schottky (like BAT4) or 40 Volt Schottky (Zetex ZHCS400 or Vishay SD103AWS ) is enough to set the switching frequency (program the clock oscillator)
The TPS40052 has independent clock oscillator and ramp generator circuits. The clock oscillator is used as the main clock for the ramp generator circuit. The switching frequency f (kHz) of the clock oscillator is set to ground by a resistor (R). The clock frequency is related to r, expressed in kΩ, from equation (1). Shortwave TT
The TPS40052 features fixed uvlo protection. Fixed uvlo monitors input voltage. The uvlo circuit keeps soft-start low until the input voltage exceeds the undervoltage threshold.

BP5 and BP10 Internal Voltage Regulators
Activation properties of BP5 and BP10 regulators. Subtle changes in BP5 depend on the switching frequency. The BP10 regulation characteristics also vary based on the load created by external MOSFET switching.
Choosing the Inductor Value The inductor value determines the amount of ripple current in the output capacitor and the load current when the converter enters discontinuous mode. Too much inductance results in lower ripple current, but for the same load current, the ripple current is physically larger. Too small an inductor will result in higher ripple current and more (or more expensive output capacitors) for the same output ripple voltage requirement. A good compromise is to choose the inductor value so that the converter does not go into discontinuous mode until the load approaches 10% to 30% of the rated output. The inductance value V is the output voltage o
is the inductor peak-to-peak current calculation output capacitor The output capacitance depends on the output ripple voltage requirements, the output ripple current, and any output voltage deviation requirements during load transients.
The output ripple voltage is a function of the output capacitor and capacitor ESR. Worst-case output ripple is given in Equation VI ESR 8 COFSW VP 1 P (3) Due to the ESR components, the output ripple voltage is typically between 90% and 95%. In the presence of load transient requirements, the output capacitance requirements typically increase. During a step load, the output capacitor must supply energy to the load (light-heavy load step) or absorb excess inductor energy (heavy-light load step) while maintaining the output voltage within acceptable limits. The capacitance depends on the size of the load step, the speed of the loop, and the size of the inductor.
Stepping the load from heavy to light will cause the output to overshoot. The excess energy stored in the inductor must be absorbed by the output capacitor. The energy stored in the inductor is the output current under heavy load conditions, I is the output current under light load conditions, and V is the final peak voltage of the capacitor f
Program soft start
The TPS40052 uses a closed-loop approach to ensure that the output is controlled during startup. Soft-start is programmed by charging an external capacitor (C) from an internally generated current source. The voltage on C is fed into a single non-inverting input to the error amplifier (except fb and ea_ref). The loop is closed at the lower value of the C voltage or the external reference voltage ea_ref. Once the C voltage rises above the external reference voltage, the regulation is based on the external reference. To ensure a controlled rise in the output voltage, the soft-start time should be greater than the equation and there is a direct correlation between the input current required during start-up. The faster T, the higher the input current required at startup. This relationship is described in more detail in the section titled "Programming Current Limit" Start-to-start SS For applications where the V supply is slowly rising (typically between 50 ms and 100 ms), it may be necessary to increase the soft-start time to approximately Between 2 ms and 5 ms to prevent unwanted UVLO tripping. The soft-start time should be longer than the time the V supply transitions between 8 V and 9 V.
Program current limit
The TPS40052 adopts a two-stage overcurrent protection method. The first layer is the pulse-to-pulse protection scheme. Current limiting is achieved on the high side FET by inducing a voltage drop across the FET when the gate is driven. Compare the MOSFET voltage with the voltage drop across the resistor connected between the VIN pin and the ILIM pin when driven by a constant current source. If the voltage drop across the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse terminates immediately. The MOSFET remains off until the next switching cycle is initiated.
The second layer includes a fault counter. The fault counter is incremented on overcurrent pulses and decremented on clock cycles without overcurrent pulses. When the counter reaches seven (7) times, a restart will be issued and seven soft-start cycles will be initiated. During this period, both the upper and lower field effect transistors are turned off. The counter is decremented on each soft-start cycle. When the counter decrements to zero, PWM is re-enabled. If the fault has been removed, the output starts normally. If the output is still present, the counter counts seven overcurrent pulses and then re-enters Layer 2 fault mode. Typical Overcurrent Protection Waveform Minimum Current Limit Set Point Current Limit Programming Resistor (R) is calculated using Equation (12). Care must be taken when choosing the values of v and i in the equation. To ensure that the output current is at the overcurrent level, the minimum value of isink and the maximum value of vos must be used. Ilim OS sink I is the current going into the Ilim pin, with a minimum value of 8.6µA. Sink i is the overcurrent setting value, which is the DC output current plus half of the inductor peak current. OCV is the overcurrent comparator offset with a maximum value of 30 mV. operating system

Layout Considerations
The PowerPad software package provides low thermal resistance for cooling the device. The PowerPad gets its name and low thermal resistance from the large pads on the bottom of the device. For maximum thermal performance, the board must have a tin-copper pad under the package. The size of this area depends on the size of the PowerPad package. For 16-pin TSSOP (PWP) package, the area is 5 mm x 3.4 mm
Thermal vias connect this area to an internal or external copper plane and should have a drilled diameter small enough to effectively plug the via when the via barrel is copper plated. During solder reflow, this plug is required to prevent the solder from being drawn away from the interface between the package and the tin solder area under the device. A 0.33mm (13 mil) drill hole diameter works well when plated with 1oz copper on the board surface, while plated through hole barrels. If the thermal vias are not plugged when copper plating is performed, the vias should be at least equal to 0.1 mm in diameter using solder mask material. This capping prevents corrosion of the solder through the thermal vias and can create solder voids under the package.
MOSFET package
The choice of MOSFET package depends on the power dissipation of the MOSFET and the expected operating conditions. Generally, for surface mount applications, DPAK type packages offer the lowest thermal impedance and therefore the highest power dissipation capability. However, the effectiveness of DPAK depends on proper layout and thermal management. Theta specified in the MOSFET datasheet refers to a given copper area and thickness. In most cases, a minimum thermal impedance of 40°C/W requires a G 8722 ; 10/FR−4 board with a square inch of 2 ounces of copper. Lowering thermal resistance can come at the expense of board area.
Layout Considerations Grounding and Circuit Layout Considerations
The TPS4005X provides separate signal ground (SGND) and power ground (PGND) pins. Circuit grounds must be properly separated. Each ground should include a plane to minimize its impedance. High power noise circuits such as output, synchronous rectifier, MOSFET driver decoupling capacitor (BP10), and input capacitor should be connected to the PGND plane of the input capacitor.
Sensitive nodes such as the FB resistor divider, R, and ILIM should be connected to the SGND plane. The sgnd plane can only make single point connections with the pgnd plane.
Component placement should ensure that the bypass capacitors (BP10 and BP5) are as close as possible to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located near high dv/dt nodes such as hdrv, ldrv, boost and switch nodes (sw).
The sw-pin Schottky diode should be close to the TPS40052 and the short, wide traces should point to pins 9 and 12.
Input Voltage: 10 Vdc to 14.4 Vdc
Output voltage: 1.25V±1% (1.2375≤VO≤1.2625)
Output current: 8 A (max, steady state), 10 A (surge, 10 ms duration, 10% duty cycle max)
Output Ripple: 33 mVP-P at 8 A
Output Load Response: 0.1 V=>10% to 90% step load change from 1 A to 7 A
Operating temperature: −40°C to 85°CF = 170 kHz shortwave