Features

Quick throughput: 250 KSPS

VDD

low power for 2.35 V to 5.25 V , 250 KSPS, 3 volt power

at 250 KSPS is 13.5 mW, 5 V power supply

Wide input bandwidth:

When the input frequency is 100 kHz, the minimum signaling of the minimum signaling noise is The ratio is 71 db

Flexible power/serial clock speed management

Pipeless delay

High -speed serial interface:

spi #174;// Qspi #8482;/micro-silk #8482;/DSP compatibility

Standby mode: maximum 1 μA

8 guide TSOT packaging

8-lead MSOP package

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123] Application

Battery power supply system:

Personal digital assistant

Medical Device

Mobile communication

Instrument and control system

]

Data acquisition system

High -speed modem

Optical sensor

General description Power consumption and dual channels approach ADC one by one. The working voltage of these components is 2.35 to 5.25 volts, and the throughput rate is as high as 250 KSPS. These components include a low -noise, wide -band -width tracking maintenance amplifier, which can process the input frequency of more than 6 MM. The conversion process and data collection are controlled by the CS and serial clocks, allowing the device to be a microprocessor or DSP interface. The input signal is sampled along the CS decrease, and the conversion is also started at this time. There is no delay in pipeline -related pipelines.

The channel to be converted through DIN pin selection, and the operating mode is controlled by CS. The serial data stream from the DOUT tube has a channel identifier, which provides information about conversion channels.

AD7911/AD7921 uses advanced design technology to achieve very low power consumption under high throughput.

The reference of the component is obtained from the VDD, so the ADC has the widest dynamic input range. Therefore, the analog input range of parts is 0 to VDD. The conversion rate is determined by the SCLK signal.

Product Highlights

1, 2 channels in TSOT packaging, 250 KSPS, 10-/12-bit ADC.

2. Low power consumption.

3. Flexible power/serial clock speed management. The conversion rate is determined by serial clock; when the speed of the serial clock increases, the conversion time is shortened. The components also have a power -off mode to maximize the power efficiency at a maximum of the low throughput. When using the power loss mode when not converted, the average power consumption is reduced. The maximum current consumption is 1 μA, which is usually in the power -off mode.

4. Reference from power supply.

5. No delay in pipeline. These components use standards to approach ADC one by one, and accurately control the sampling moment through CSINPUT and ONCE-OFF conversion.

Function box diagram

Time example

Figure 6 Figure 7 shows some timed parameters of the timing specification.

Timing Example 1

As shown in FIG. 7, when FSCLK u003d 5MHz, throughput is 250KSPS, the cycle time is:

] When T2 u003d 10ns, TACQ is 1.49μs, which meets the requirements of TACQ 290ns.

In FIG. 7, TACQ consists of 2.5 (1/FSCLK)+T10+Tquiet, where the maximum value of T10 u003d 30NS. This allows the value of TQUIET to 960 ns to meet the minimum requirements of 30 ns.

Timing Example 2

AD7921 can also work at a lower clock frequency. As shown in Figure 7, when FSCLK u003d 2MHz and the throughput is 100KSPS, the cycle time is:

T2 u003d 10ns, TACQ is 3.74μs, which meets the TACQ 290nsS of 290ns Require.

In FIG. 7, TACQ consists of 2.5 (1/FSCLK)+T10+Tquiet, where the maximum value of T10 u003d 30NS. This allows the value of TQUIET to be 2.46 μs to meet the minimum requirements of 30 ns.

In this example, the signal may have been obtained before the conversion is completed as the slower clock value, but it still needs to leave the minimum value of 30 ns between the conversion. In this example, the signal should be completely collected at about point C in Figure 7.

Term

Points non -linearity

The maximum deviation of the straight line of the point point of the function through the ADC. For AD7911/AD7921, the endpoint of the transmission function is zero standard, that is, 1 l under the first code conversionSB point, and full scale, that is, the point of the last code conversion 1LSB.

Fortune non -linearity

The difference between the measurement value and the ideal 1 LSB changes between any two adjacent code in ADC.

The offset error

The deviation of the first code conversion (00 ... 000) to (00 ... 001) is the deviation from the ideal value, that is, Agnd+1 LSB.

The offset error matching

The difference between the offset error between any two channels.

gain error

The last code conversion (111 ... 110) to (111 ... 111) is deviated with the ideal value, that is, vRF 1 lsb.

The gain error matching

The difference between the gain error between the two channels.

Total non -adjustment error

Including comprehensive specifications of gain error, linear error, and offset error.

Channel isolation

Conversion of the stringing level between channels. By applying 20 kHz to 500 kHz full -standard sine wave signals to non -selected input channels, and determining the signal to measure the degree of 10 KHz signal attenuation in the selected channel. This number gives the worst situation of the two channels of AD7911/AD7921.

Tracking and maintaining the collection time

After the conversion is over, the output of the tracker reached the time required for its final value within ± 1 LSB. The tracking kernels return to the tracking mode at the end of the conversion. For more details, see the serial interface part.

The signal -to -noise ratio and distortion ratio (Sinad)

The signal -to -noise ratio and distortion rate measured at the output end of the A/D converter. The signal is the average root value of the sine waves, and the noise is the sum of the equity root value of all non -basic signals. Half of the sampling frequency (FS/2), including harmonics, does not include DC electricity.

signal -to -noise ratio

The signal -to -noise ratio measured at the output end of the A/D converter. The signal is the RMS value entered by a sine wave. The noise is the measuring root quantification error in the NYQUIST bandwidth (FS/2). The RMS value of the sine wave is half of its peak value, and the RMS value of the quantitative noise is Q/√12. This ratio depends on the quantitative level in the digitalization process; the more levels, the smaller the quantitative noise. For the ideal N -bit converter, SNR is defined as

SNR u003d 6.02 N+ 1.76 DB

Therefore, for the 12 -bit converter The signal -to -noise ratio is 62 dB.

However, various errors in ADC cause the measurement signal ratio to be measured less than the theoretical value. These errors are caused by points and differential non -linearity, internal communication noise sources.

Total harmonic distortion (THD)

The ratio of the equity of the harmonic and the ratio of the base wave is defined as:

In the formula:

V1 is the average root amplitude of the Koba.

V2, V3, V4, V5, and V6 are the average root amplitude of the second to sixth harmonic.

Peak harmonics or strange noise

ADC output spectrum in the second largest component of the measuring equally root value (Gundam FS/2, excluding DC electricity) and the basis root value of the base wave Ratio. Under normal circumstances, the value of this specification is determined by the largest harmonic in the spectrum, but this is a peak of noise for the ADC buried in the noise layer.

Mutual distortion

When the input consists of a sine wave of two frequencies (FA and FB), any non -linear active device will be in the harmony and difference of the MFA ± NFB Frequent distortion products, where M, n u003d 0, 1, 2, 3, are pushed according to this. Mutual disturbances refer to the items that M and N are not equal to zero. For example, the second order includes (FA+FB) and (FA FB), and the third -order item includes (2FA+FB), (2FA FB), (FA+2FB), (FA ; 2FB).

AD7911/AD7921 uses the CCIF standard for testing, wherein the two input frequency (see FA and FB in the ""specifications"" section). In this case, the frequency of the second -order item is usually far from the original sine wave, and the frequency of the third -order item is usually close to the input frequency. Therefore, second -order and third -order items are separated. The real calculation of interoperability distortion is as described in the THD specification, which is defined as the RMS of a single distortion product and the basic principles expressed in the decibel.

Typical performance features

Figure 10 and 11 show the typical FFT diagram of AD7921 and AD7911 at 250 KSPS sampling rate and 100 kHz input frequency.

FIG. 12 shows the relationship between AD7921 with 250KSPS and the SCLK frequency is 5MHz. The relationship between the SINAD ratio of different power supply voltage and the input frequency.

FIG. 13 shows the signal -to -noise ratio performance and input frequency of 250 KSPS at different power supply voltage, the SCLK frequency is 5 MHz, which is suitable for AD7921.

FIG. 14 and Figure 15 show the INL and DNL performance of AD7921.

FIGDuring the sampling rate of the power supply voltage and 250KSPS, the relationship diagram of the total harmonic distortion of different sources and the analog input frequency under different sources. See the simulation input section.

FIG. 17 shows the relationship diagram of the total harmonic distortion and analog input frequency when the 250 KSPS and 5 MHz SCLK frequency are sampled.

FIG. 18 shows the relationship between the shutdown current at different working temperature and the power supply voltage.

Circuit information

AD7911/AD7921, respectively, 2 channels, 10-/12-bit, single power supply, modular number, digital number Converter (ADC). These components can work under 2.35 volt to 5.25 volts. When a 5 volts or 3 volt power supply is powered, the AD7911/AD7921 can reach 250 KSPS when equipped with a 5 trillion clock. AD7911/AD7921 provides users with a film tracking and holding, ADC and serial interface, all of which are encapsulated in a small 8 -line TSOT package or 8 -line MSOP package, which provides users with more than others than others. The solution saves the advantages of space. The serial clock inputs the data from the component, controls the data transmission of the ADC, and provides the clock source to the ADC one by one. The analog input range is 0 to VDD. ADC does not require external reference, nor does it require reference on the chip. The benchmark of AD7911/AD7921 comes from the power supply, so it can provide the widest dynamic input range.

AD7911/AD7921 has a power -off option, allowing power to save power between conversion. The power -off function is implemented through the standard serial interface, as described in the operation mode.

Inverter operation

AD7911/AD7921 is 10-/12 bits approaching ADC based on charge-based re-assigned DAC. Figure 19 and 20 show the simplified schematic diagram of ADC. Figure 19 shows the ADC in the collection phase. SW2 is closed, SW1 is in position A, the comparator is kept in a balanced state, and the sampling capacitor obtains the signal on the selected VIN channel.

When the ADC starts to convert (see Figure 20), SW2 is opened, and SW1 moves to position B, causing the comparator to become unbalanced. Control logic and charge reenging DACs are used to increase or decrease fixed amounts of charge from sampling capacitors to return the comparator back to the balance. When the comparator is re -balance, the conversion is completed. Control logic to generate ADC output code. Figure 21 shows the ADC transmission function.

ADC transmission function

AD7911/AD7921 output encoding is direct binary. Design code conversion occurs in the companyThe continuing integer LSB value, that is, 1 LSB, 2 LSB, push according to this. For AD7921, LSB size is VDD/4096, for AD7911, LSB size is VDD/1024. The ideal transmission characteristics of AD7911/AD7921 are shown in Figure 21.

Typical wiring chart

Figure 22 shows the typical connection diagram of AD7911/AD7921. VREF is obtained from the VDD, so VDD should be decoupled well. This provides an analog input range from 0 V to VDD. The conversion result is output in 16 digits, including two front -guide zero, followed by the channel identification symbols of the recognition transition channel, the invalid position that matches the conversion channel, and then a 12 -bit or 10 -bit MSB. After the results of AD7911, 10 bits follow two 0. See the serial interface part.

In addition, due to the very low power supply current required by AD7911/AD7921, the precision benchmark can be used as the power supply of AD7911/AD7921. Ref19X reference voltage (Ref195 for 5V or Ref193 for 3V) can be used to provide ADC with the required voltage (see Figure 22). If the power supply is very noisy or the system's power supply voltage is not a value of 5 V or 3 V (for example 15 V), this configuration is particularly useful. Ref19X outputs a stable voltage to AD7911/AD7921. If you use a low pressure difference Ref193, the current supply of power supply to AD7911/AD7921 is usually 1.5 ma. When ADC is converted at a rate of 250 KSPS, the REF193 needs to provide AD7911/AD7921 with a maximum 2 MA current. Ref193's load adjustment is usually 10 PPM/MA (Ref193, VS u003d 5 V), and the 2 mA error generated is 20 PPM (60 μV). For this error, LSA is 0821.0, corresponding to AD792 VDD u003d 3 V from Ref193, and the LSB error of AD7911 is 0.061.

For applications that need to consider power consumption, the power -off mode of ADC and the dormant mode of the REF19X benchmark should be used to improve the power performance.

Table 6 provides some typical performance data. Under the same setting conditions, various reference values u200bu200bare used as VDD sources and 50 kHz input sound.

The analog input

Figure 23 shows the equivalent circuit of AD7911/AD7921 analog input structure. Two diode D1 and D2 provide ESD protection for simulation input. It must be noted that the analog input signal will not exceed 300 millivol to the power rail, because this will cause these twoThe polar pipe is pressed forward and starts to conduct current to the substrate. The maximum current that these diodes can transmit them can be transmitted by 10 mAh when they do not cause irreversible damage to parts.

The capacitor C1 in FIG. 23 is usually about 6 PF, which is mainly due to pipe capacitors. The resistor R1 is a concentrated component composed of the guide resistance of the tracking and the switch. It also includes the input resistance of the multi -way relicant. The resistance is usually about 100Ω. Capacitor C2 is an ADC sampling capacitor, usually with a capacitor of 20PF.

For communication applications, it is recommended to use the tape filter on the related simulation input pins to remove the high -frequency component from the analog input signal. In applications where harmonic distortion and signal -to -noise ratio are very important, the simulation input should be driven by low impedance sources. Large source impedance will significantly affect the ADC's communication performance. This may need to use input buffer amplifiers. The choice of computing amplifier is a specific application function.

Table 7 provides some typical performance data. Under the same setting conditions, various op amp are used as input buffer, and the input tone is 50kHz.

When no amplifier is used to drive analog input, the source impedance should be limited to low value. The maximum source of impedance depends on the tolerance total harmonic distortion (THD). THD increases with the increase of source impedance and decrease in performance (see Figure 16).

Digital input

Digital input applied to AD7911/AD7921 is not limited by restricted simulation input. Instead, the number of digital inputs can reach 7V, and it is not limited by VDD+0.3V as an analog input. For example, if AD7911/AD7921 works under 3 V VDD, the 5 V logic level can be used for digital input. However, it is worth noting that when VDD u003d 3V, the data output on DOUT still has a 3V logic level. Another advantage of SCLK, DIN, and CS is not limited by VDD+0.3V restrictions. This is a avoiding problem of power sorting. If CS, DIN, or SCLK is applied before VDD, there is no risk of lock locks like a signal greater than 0.3V before VDD.

DIN input

The passage to be converted in the next conversion is selected by writing DIN pin. The data on the DIN pins is loaded to the AD7911/AD7921 dropped by SCLK. While reading the conversion result from parts, the data is transmitted to the parts that is transmitted to the DIN pin.

Use only the third place of the DIN word; the remaining ADC is ignored. The third MSB is the channel identifier. It indicates the channel to be converted in the next conversion, VIN0 (CHN u003d 0) or vin1 (chn u003d 1).

Output

The conversion results from AD7911/AD7921 are provided on the output as serial data stream. While conversion, these positions are output along the upper clock in SCLK.

The serial data stream of AD7921 consists of two precursors, and the position of the channel converted by the logo is invalid to match the channel logo position, and the 12 -bit conversion result of the MSB first provides MSB.

For the AD7911, the serial data stream consists of two front -guide zero, and the position of the channel converted by the logo is invalid to match the channel logo position, and the 10 -bit conversion result of the MSB first, then two two, then two two, then two are two. Followed zero.

The operating mode

The two working modes of AD7911/AD7921 are normal mode and power -off mode. Select the operation mode by controlling the logical state of the CS signal. After the converting initialization, CS is raised to determine whether the AD7911/AD7921 enters the power -off mode. Similarly, if you are already in the power -off mode, CS can control whether the device will restore normal operation or keep the power -off mode.

The power -off mode is designed to provide flexible power management options and optimize the power consumption and throughput ratio for different application requirements.

Normal mode

The normal mode aims to obtain the fastest throughput performance. Users do not have to worry about any power -on time, because AD7911/AD7921 has always been fully powered. Figure 26 shows the operation of AD7911/AD7921 in this mode.

Converted at the beginning of the CS, as described in this section. In order to ensure that the components are always fully powered, the serial interface ECS must be maintained at a lower level, and at least 10 SCLK decreases by the CS decrease. If CS becomes high at any time before the tenth SCLK decreases, but the part is kept in power at any time before the end of the conversion, but the conversion is terminated, and DOUT returns three states. For AD7911/AD7921, at least 14 and 16 serial clock cycles are required to complete the conversion and access the complete conversion results.

CS can be high until the next conversion, or you can return to the high level until CS is the next conversion (actually idle CS Low). Once the data transmission is complete (the dough returns to three states), you can start another conversion by introducing CSLOW again after the quiet time TQUIET.

Power off mode

The power -off mode is suitable for applications that require slower throughput. In each conversion process of ADC, or turn off the throughput of ADC within a longer period of time, or convert it at a higher rate between ADCs to several timesBetween the outbreak. When AD7911/AD7921 is in the power -off mode, all analog circuits are powered off.

To enter the power failure mode, the conversion process must be interrupted at any time before the second decline edge of SCLK and the 10th decrease edge of SCLK, as shown in Figure 27. Once the CS is raised in the SCLKS window, the component enters the power -off mode, and the conversion of the CS decline along the start is terminated, and DOUT returns to three states. If CS becomes higher before the second SCLK decreases, the parts will remain in normal mode and will not be powered off. This helps to avoid accidental power off due to the CS line failure.

To withdraw from this operation mode and connect the power of AD7911/AD7921 again, it will execute virtual conversion. At the decline of the CS, the device starts to power. As long as the CS remains at a lower level, the device will continue to power on the equipment until the 10th SCLK declines edge. Once the 16 SCLK and the next conversion get valid data, the device is fully powered, as shown in Figure 28. If the CS before the 10th decrease of SCLK is at a high level, the AD7911/AD7921 will return the power -off mode. This helps to avoid accidental power due to the accidental sudden emergencies of the 8 SCLK cycle when the CS line is faulty or the CS is low. Therefore, although the device may start power at the decline of the CS, it is disconnected again at the rising edge of the CS, as long as this occurs before the 10th SCLK decline edge.

Powering time

AD7911/AD7921's power In the case of 5MHz, a virtual cycle is always enough to power the equipment. Once the virtual cycle is completed, the ADC will be fully powered and the input signal is correctly obtained. Static time TQUIET must still allow the next point from virtual conversion to CS to return to three states. When running at 250 KSPS, AD7911/AD7921 is powered on and signals in ± 1 LSB within a virtual cycle.

As shown in Figure 28, when the virtual cycle is powered on from the power -off mode, it is tracked and kept back to the CS decrease when the component is powered off. The tracking mode along the top. Display as point A in the middle. At this time, the parts begin to obtain the signal on the channel selected in the current pseudo -conversion.

Although a virtual cycle is sufficient to power the device and obtain VIN at any SCLK frequency, it does not necessarily mean that it must always pass through the complete virtual cycle of 16 SCLK to power and fully obtain VIN. 1 μs is enough to power the device and obtain the input signal. For example, if you apply 5 MHz SCLK frequency to ADC, the cycle time is 3.2 μs. In a virtual cycle (3.2 μs), parts will be powered on and fully obtained VIN. However, after using 1 μs of 5MHz SCLK, only 5 SCLK cycles have been passed. At this stage, ADC will be fully powered. In this case, CSC can increase after the 10th SCLK decline, and decrease again after a period of time. TQUIET to start the conversion. When the power supply is first applied to AD7911/AD7921, the ADC can be powered on in the power failure mode or normal mode. Therefore, it is best to allow a virtual cycle to ensure that parts are fully powered before trying effective conversion. Similarly, if the user wants to keep the component power off mode when not in use and power in the power off mode, the virtual cycle can be used to ensure that the device is in the power off mode by executing the loop shown in Figure 27.

Once powers to AD7911/AD7921, the power -on time is the same as when power -off mode. In normal mode, the component is fully power -based about 1 μs. Before performing a virtual cycle, no need to wait 1 μs to ensure the required operation mode. Instead, after power supply to ADC, the fake cycle can occur directly. If the first effective conversion is executed after the virtual conversion, you must pay attention to ensure that sufficient collection time is allowed. When the ADC is for the first time after the power is turned on, tracking and maintaining a state. It returns to the fifth SCLK on the back of the CS to drop the trajectory of the fifth SCLK.

Power and throughput

By using the power -off mode on the AD7911/AD7921 when not converted, the average power consumption of ADC decreased lower at a lower throughput. Figure 29 shows how the device maintains a longer period of time when the throughput is reduced, and over time, the average power consumption is reduced accordingly.

For example, if AD7911/AD7921 is working on a continuous sampling mode of 5MHz SCLK (VDD u003d 5V) with a throughput of 50KSPS and placing the device in the power off mode between the conversion, the power consumption calculation is as follows as follows Essence The power consumption during normal operation is 20 mW (VDD u003d 5 V). If a virtual cycle is powered between the conversion (3.2 μs), and the remaining conversion time is another cycle (3.2μs), then AD7911/AD7921 consumes 20 mW in each conversion cycle and lasts 6.4 μs. If the throughput is 50 KSPS and the cycle time is 20 μs, the average power consumed per cycle is:

If VDD u003d 3V, SCLK u003d 5MHz, and the equipment is conversion The power reduction mode is once again, and the power consumption during normal operation is 6MW. In each conversion cycle, AD7911/AD7921 now disperse 6 mW and lasts 6.4 μsEssence When the throughput is 50KSPS, the average power consumed per cycle is:

In the previous example The shutdown current is very low, so it will not have any impact on the overall power consumption value. Figure 29 shows the relationship between the power consumption and throughput when using the power -off mode between the 5V and 3V power supply.

The power failure mode is suitable for the situation of the throughput of about 120 KSPS and below, because the higher sampling rate will not save electricity in the power off mode.

Serial interface

Figure 30 and Figure 31 show the detailed time -sequential diagram of AD7921 and AD7911 serial interfaces, respectively. The serial clock provides a conversion clock and controls information transmission from AD7911/AD7921 during the conversion period.

CS signal starts the data transmission and conversion process.

The decline of the CS will be tracked and kept in the maintenance mode, so that the bus is exit three states. At this time, the simulation input is sampled and the conversion is started.

For AD7921, the conversion requires 16 SCLK cycles to complete. Once the 13 SCLK decreases, Trackand Hold will return to the trajectory on the next SCLK rising edge, as shown in point B in Figure 30. On the bottom of the 16th SCLK, the DOUT line will return to three states. If the rising edge CS occurs before 16 SCLK, and then the conversion is terminated, the DOUT row returns to three states. Otherwise, DOUT returns to 3 states at the 16th SCLK falling edge, as shown in Figure 30. The execution process and access data from AD7921 require 16 serial clock cycles.

For AD7911, the conversion requires 14 SCLK cycles to complete. Once the 13 SCLK decreases, Trackand Hold will return to the trajectory on the next SCLK rising edge, as shown in point B in Figure 31.

If the CS rising edge appears before 14 SCLK, the conversion is terminated, and the DOUT line returns to three states. If 16 SCLKs are considered in the cycle, DOUT returns to 3 states at the 16 SCLK decline edge, as shown in Figure 31.

CS enters the low clock. Then, the subsequent SCLK decrease from the second pre -guide zero to output the remaining data. Therefore, the first decrease on the serial clock has the first front guide provided by the edge of the clock and returned the second front guide to the clock output. The last one in the data transmission was valid in the 16th decline edge, and the previous decrease of the first (15th) decrease was punch -in.

Using slower SCIn the LK application, you can read the data on the edge of each SCLK. In this case, SCLK's first drop along the clock output is the second ahead of time, and it can be read on the first rising edge. However, the first front guide is unless the first decline is not read, and the clock will be lost when the CS becomes lower. SCLK's 15th drop is the last bit along the clock, which can be read on the edge of the 15th rising SCLK.

If the CS becomes low after the SCLK drops, the CS outputs the first front guide zero as before, and can be read in the SCLK rising edge. The next SCLK drops the second front guide along the clock, it can be read on the next rising edge.

microprocessor interface

AD7911/AD7921 The serial interface allowed components to be directly connected to a series of microprocessors. This section introduces how to connect AD7911/AD7921 with some more common microcontrollers and DSP serial interface protocols.

AD7911/AD7921 to TMS320C541 interface

The serial interface on TMS320C541 uses continuous serial clock and frame synchronization signals to synchronize data transmission operations with peripheral equipment such as AD7911/AD7921. CS input allows simple interfaces between TMS320C541 and AD7911/AD7921 without any adhesive logic. The serial port of the TMS320C541 is set to work in an emergency mode (the serial port control register SPC FSM u003d 1), the internal serial clock CLKX (MCM u003d 1 in the SPC register), and the internal frame signal (in the SPC register Txm u003d 1); therefore, both pins are configured to output. For AD7921, the word length should be set to 16 bits (FO u003d 0 in SPC registers). This DSP allows only frames with 16 -bit or 8 -bit frames. Therefore, in AD7911, when 14 bits are needed, the FO bit should be set to 16 bits and 16 SCLK. For AD7911, in the last two clock cycles, two tails were output by clock.