Conversion time 10 to 10 bit resolution ADC programmable power down mode I'm sorry. 1.2.7 V dc to 5.5 V dc wide range single supply operation 0 V to VCC built-in analog multiplexer, 8 analog input channels TMS320 DSP and microprocessor SPI and QSPI compatible serial interface in self-test mode, Extended Sampling Hardware I/O Clock Phase Adjust Input Programmable Power and Slew Rate Asynchronous Start Slew Description
The TLV1544 and TLV1548 are CMOS 10-bit switched capacitor successive approximation (SAR) analog-to-digital converters. Each device has a chip select (CS), input-output clock (I/O CLK), data-in (data-in), and serial data-out (data-out), providing direct 4-wire synchronous serial from the host microprocessor Peripheral Interface (SPI 63722;, QSPI 63722;) port. When interfacing with a TMS320 DSP, an additional frame sync signal (fs) indicates the start of a serial data frame. These devices allow high-speed data transfer from the host. The INV CLK input provides further timing flexibility for the serial interface.
In addition to a high-speed converter and versatile control capabilities, the device has an on-chip 11-channel multiplexer that can select any of eight analog inputs or any of three internal self-test voltages. The sample-and-hold function is automatic, except for the extended sample period, which is initiated by the falling edge of asynchronous CStart. At the end of the A/D conversion, the end-of-conversion (EOC) output goes high, indicating that the conversion is complete. The TLV1544 and TLV1548 are designed to operate over a wide range of supply voltages with very low power consumption. Power saving is further enhanced by software programmable power down modes and slew rates. The converters in this unit have different high-impedance reference inputs that help with scaling, scaling, and isolation of analog circuits from logic and power supply noise. The switched capacitor design allows low error conversion over the entire operating temperature range.

Description (continued)
The TLV1544 has four analog input channels, while the TLV1548 has eight analog input channels. The TLV1544C and TLV1548C are characterized for operation over a temperature range of 0°C to 70°C. The TLV1544I and TLV1548I feature operation over the full industrial temperature range of -40°C to 85°C. The TLV1548M is characterized for operation over the full military temperature range of -55°C. o 125 degrees Celsius.
Functional block diagram

DETAILED DESCRIPTION Initially, when CS is high (inactive), the data input and input/output CLK are disabled and the data output is in a high impedance state. When the serial interface receives CS low (active), the conversion sequence begins with enabling the I/O CLK and data inputs and removing data from the high-impedance state. The host then provides the 4-bit channel address to the data input and the I/O clock sequence to the I/O CLK. During this transfer, the host serial interface also receives the previous conversion result from the data output. The I/O CLK receives an input sequence from the host that is 10 to 16 clocks in length. The first four valid I/O CLK cycles load the input data register with the 4-bit input data on data to select the desired analog channel. The next six clock cycles provide control time for sampling the analog input. The sampling of the analog input is held after the first valid I/O CLK sequence of ten clocks. The tenth clock edge also turns EOC low and begins the conversion. The exact location of the I/O clock edge depends on the mode of operation.
serial interface
The TLV1548 is compatible with general-purpose microprocessor serial interfaces such as SPI and QSPI and the TMS320 DSP serial interface. The internal latch flag if_pattern is generated by sampling the fs state on the falling edge of CS. When fs is high on the falling edge of cs, if_mode is set to 1 (for microprocessors), when fs is low on the falling edge of cs, if_mode is cleared to 0 (for dsp). This flag controls I/O CLK multiplexing and state machine reset functions. When interfacing with a microprocessor, fs is pulled high.

I/O Clock When fast input/output is possible, the I/O CLK can be as high as 10 MHz over most voltage ranges. For a supply voltage range of 2.7 V, the maximum I/O CLK is limited to 2.8 MHz. Table 1 lists the maximum I/O CLK frequencies for all different supply voltage ranges. It also depends on the input source impedance. For example, I/O CLK speeds higher than 2.39 MHz can be achieved if the input source impedance is less than 1 kΩ.
Table 1. Maximum I/O CLK Frequency
VCC maximum input resistance (max)
Source Impedance Input/Output Clock
27V 5km
1 kΩ 2.39 MHz
2.7V 5K
100 ohms 2.81 MHz
45V 1k
1 kΩ 7.18 MHz
4.5 volts 1 kV
100 Ohm 10 MHz Microprocessor Serial Interface When the device is in microprocessor interface mode, if INV CLK is held high, incoming data bits from the data input are clocked on the first four rising edges of the I/O CLK sequence. If INV CLK is held low, incoming data bits are clocked on the first four falling edges of the I/O CLK sequence. The MSB of the previous conversion appears on data out on the falling edge of cs. The remaining 9 bits are shifted out on the next 9 edges of I/O CLK (depending on the state of INV CLK). 10 bits of data are transferred to the host through the data output.
At least 9.5 clock pulses are required for conversion to start. On the tenth clock rising edge, the EOC output goes low and returns to a high logic level after the conversion is complete; the host can then read the result. On the tenth falling clock edge, internal logic takes data low to ensure that the remaining bit values are zero if the I/O CLK transfer is more than ten clocks long.
CS is inactive (high) between serial I/O CLK transfers. Each transfer requires at least 10 I/O CLK cycles. The falling edge of CS starts the sequence by removing data from the high impedance state. The rising edge of CS ends the sequence by returning the data to a high-impedance state within the specified delay time. Additionally, the rising edge of CS disables the I/O CLK and data input for the set time. Conversion does not begin until the tenth I/O CLK rising edge.
During an ongoing loop, a high-to-low transition on CS for the specified time will abort the loop and the device will return to its initial state (the output data register retains the previous transition result). Since the output data may be corrupted, cs should not be taken low until the conversion is complete.

DSP interface
The TLV1544/1548 can also interface with the TMS320 family of DSPs through the serial port. The analog-to-digital converter (ADC) is a slave device where the DSP provides fs and serial I/O CLK. Send and receive operations are concurrent. The falling edge of fs must occur within seven I/O CLK cycles after the falling edge of cs.
The difference between the DSP I/O cycle and the microprocessor I/O cycle is as follows:
When interfacing with a DSP, the output data MSB is available after fs↓. The remaining output data changes on the rising edge of I/O CLK. Input data is sampled on the first four falling edges of I/O clk after fs↓ and when inv clk is high, or after fs↓ and when inv clk is low. When interfacing with a microprocessor, this operation is reversed.
After the rising edge of FS, a new DSP I/O cycle begins on the rising edge of I/O CLK. When fs is high, the internal state machine is reset on every falling edge of I/O CLK. When interfacing with a microprocessor, this operation is reversed.
When interfacing with a DSP, the TLV1544/1548 supports 16 clock cycles. When running in DSP mode, the output data is padded with 6 trailing zeros.

Input Data Bits The data input is internally connected to a 4-bit serial input data register. Input data to select different modes or select different analog input channels. The host provides the MSB to the data word first. Each data bit is clocked on the edge of the I/O CLK sequence (rising or falling depending on the state of INV CLK and FS). Input clock can be inverted by grounding INV CLK
TLV1544/1548 Software Programming Operation Mode Input Data Byte Function Selection A3–A0 Comments Binary Hexadecimal
Analog channel a0 of TLV1548 selected 00000b 0h channel 0 for TLV1544
Analog channel A1 for TLV1548 selected 0001B 1H
Analog channel A2 for TLV1548 select 0010B 2H channel 1 for TLV1544
Analog channel A3 for TLV1548 selected 0011B 3H
Analog channel A4 for TLV1548 select 0100B 4H channel 2 for TLV1544
Analog channel A5 for TLV1548 selected 0101B 5H
Analog channel A6 for TLV1548 select 0110B 6H channel 3 for TLV1544
Analog channel A7 for TLV1548 select 0111B 7H
Software power-down setting 1000B 8H no conversion result (any access clear)
Fast conversion rate (10 microseconds) set 1001B 9H no conversion result (set to fast clear)
Slow slew rate (40µs) set 1010B Ah no slew result (cleared by setting to slow) Self test voltage (VREF – VREF –) / 2 select 1011B BH output result = 200H Self test voltage VREF select 1100B CH output result =000H self-test voltage VREF select 1101B DH output result = 3FFH reset rved 1110b eh no conversion result reserved 1111b fh no conversion result analog input and internal test voltage
The 11-channel multiplexer selects 8 analog inputs and 3 internal test inputs based on the input data bits, as shown in Table 3. The input multiplexer is a break-before-make type to reduce input-to-input noise injection due to channel switching.
The device can work in two different sampling modes: normal sampling mode (fixed sampling time) and extended sampling mode (flexible sampling time). When CStart is held high, the device operates in normal sampling mode. When operating in normal sampling mode, sampling of the analog inputs begins with the rising edge of the fourth I/O CLK pulse in microprocessor interface mode (in DSP interface mode, the fourth falling edge of I/O CLK ). Sampling lasts 6 I/O CLK cycles. In microprocessor interface mode, samples are held on the falling edge of the tenth I/O CLK pulse. In DSP interface mode, the sample is held on the falling edge of the tenth I/O CLK pulse, the three test inputs are applied to the multiplexer, and then sampled and converted in the same manner as the external analog input.

Converters The CMOS threshold detectors in successive approximation conversion systems determine the value of each bit by examining the charge on a series of binary-weighted capacitors (see Figure 1). During the first stage of the conversion process, the analog input is sampled by closing the SC switch and all ST switches simultaneously. This action charges all capacitors to the input voltage.
In the next stage of the conversion process, all ST and SC switches are turned on and the threshold detector begins to identify bits by identifying the charge (voltage) on each capacitor relative to the reference voltage. In the switching sequence, each of the 10 capacitors is checked until all 10 bits are identified, then the charge conversion sequence is repeated. In the first step of the conversion phase, the threshold detector looks at the first capacitor (weight = 512 ). Node 512 of this capacitor is switched to the REF+ voltage and the equivalent nodes of all other capacitors on the ladder are switched to REF–. If the voltage at the summing node is greater than the threshold detector's trigger point (about half of VCC), there is a bit 0 in the output register, and the 512-weight capacitor switches to REF–. If the voltage at the summing node is less than the trigger point of the threshold detector, a bit 1 is placed in the register, and the 512 weight capacitor remains connected to ref+ through the remainder of the subsequent approximation process. Repeat this process for 256-weight capacitors, 128-weight capacitors, etc. until all bits are counted.
In each step of the successive approximation process, the initial charge is redistributed among the capacitors. The conversion process relies on charge redistribution to calculate and trade off bits from MSB to LSB.

Extended Sampling, Start Sampling Asynchronously: The CStart Operation Extended Sampling mode of operation programs the acquisition time (TACQ) of the sample-and-hold circuit. This allows the device's analog inputs to be connected directly to a wide range of input source impedances. Extended sampling mode consumes higher power based on the duration of the selected sampling period.
CStart controls the sampling period and starts the conversion. The falling edge of CStart starts the sampling period of the preset channel. The low time of CSTART controls the acquisition time of the input sample and hold circuit. Samples are held on the rising edge of CSTART. Assert CStart causes the converter to perform a new signal sample on the preset active MUX channel (one of the eight channels) and discard the current conversion result ready for output. Sampling continues as long as CStart is active (negative). The rising edge of CStart ends the sampling period. The conversion cycle starts two internal system clocks after the rising edge of CStart.
Once the conversion is complete, the processor can start a normal I/O loop to read the conversion result and set the mux address for the next conversion. Since the internal flag asyncFlag is set high, this flag setting indicates that the loop is an output loop, so no conversion is performed during the loop. The internal state machine tests AsyncFlag on the falling edge of CS. AsyncFlag is set high on the rising edge of CStart and resets low on each rising edge of CS. The conversion period will follow the sampling period only if AsyncFlag tests low on the falling edge of CS. Asynchronous I/O cycles can be removed by two consecutive normal I/O cycles.

Extended Sampling Period Extended Sampling Operation Reference Voltage Inputs There are two reference inputs for the TLV1544/TLV1548, REF+ and REF–. These voltage values establish the upper and lower limits of the analog input, resulting in full-scale and zero-scale readings, respectively. The value of Ref+Ref- and the analog inputs should not exceed the positive supply or go below GND in accordance with the specified Absolute Maximum Ratings. When the input signal is at or above the reference +, the digital output is at full scale; when the input signal is at or below the reference -, the digital output is at zero.
Programmable Slew Rates When high-speed operation is not required, the TLV1544/TLV1548 offer two slew rates to maximize battery life. The slew rate is programmable. Once a slew rate is selected, it takes effect immediately within the same cycle and remains at the same rate until another rate is selected. The slew rate should be set at power up. Activation and deactivation of the power-down state (digital logic activation) has no effect on the preset slew rate.

Programmable Power-Down State By writing 8h data, the device enters a shutdown state. During the next active access, the power-on state is restored by pulling CS low. The slew rate selected before the device enters the shutdown state is not affected by the shutdown mode. Power down allows for lower power consumption. This is because continuous power (when not converting) is only 1.3 mA maximum and standby power is only 1 microamp maximum. (By averaging, power consumption can be well below 1 mA peak when conversion throughput is low.)

After power up and initialization, if operating in DSP mode, CS and FS must start the I/O cycle from high to low. EOC is initially high and the input data register is set to all zeros. The contents of the output data registers are random and the first conversion result should be ignored. For initialization during operation, CS is set high and returned low to start the next I/O cycle. The first transition after the device returns from off state may be invalid and should be ignored.
When the device is first powered up, the slew rate must be programmed and the internal asynchronous flag must be lowered once. Then, the rising edge of CS in the same cycle sets the asynchronous flag low.

Power-up initialization input clock inversion –INV CLK
The input data register uses the I/O CLK as the source of the sample clock. This clock can be reversed to provide more setup time. inv clk can invert the clock. When INV CLK is grounded, the input clock to the data register is inverted. This allows an additional half I/O CLK cycle for the input data setup time. This is useful for some serial interfaces. When the input sampling clock is inverted, the output data changes while sampling the input data.