The DF1706 's system clock can be supplied via an external clock signal at XTI (pin 6), or via the on-chip crystal oscillator. The system clock rate must be running at 128FS, 192fS, 256fS, 384fS, 512fS or 768fS, where fS is the audio sample rate. When a 128fS or 192fS system clock is applied to the DF1706, the oversampling ratio (OSR) of the DF1706 digital filter should be 4 times, not 8 times. The OSR can be selected in software mode by the hardware mode of the x4 pin (pin 21) in the MODE 2 register or by the x4 bit. It should be noted, however, that the 768fS system clock cannot be used when fS is greater than 48kHz. Both 128FS and 192fS system clocks can be used when fS is greater than 96kHz. Additionally, the on-chip crystal oscillator is limited to a maximum frequency of 24.0MHz Quincy. Table I shows sample rates for typical system clock frequency selections. The DF1706 includes a system clock detection circuit, which determines that the system clock rate is in use. This circuit compares the frequency with the system clock input (XTI) rate of the LRCIN input to determine the system clock multiplier. Ideally, LRCIN and BCKIN should be derived from the system clock to ensure proper synchronization. If the phase difference between the BE-tween system clock and LRCIN is greater than ±4-bit clock (BCKIN) period, the system synchronization and LRCIN clock will be automatically performed by the DF1706. See Figure 1 for the timing requirements for the system clock input.

figure 1

DF1706 also has internal power-on reset circuit and reset pin RST (pin 14) for providing an external reset signal. Internal power-on reset is performed automati- when power is applied to the DF1706, as shown in Figure 2. The RST pin can be used to synchronize the DF1706 with a system reset signal, as shown in Figure 3. During power-on reset (1024 system clocks), the outputs of BCKO, DOL and DOR are forced low and the output of WCKO is forced high. For an external forced reset, the BCKO, DOL and DOR outputs are forced low and the WCKO output is forced high during the initialization process (1024 system clocks), then low to high after a high transition of the RST pin (see image 3) .

figure 2

image 3

PCB Layout Guidelines

In order to obtain the specified performance from the DF1706 and its associated D/A converter, proper printed circuit board layout is critical. Figure 4 shows two methods for obtaining the best audio performance. Figure 4(a) shows a standard, mixed-signal layout scheme. The board is divided into digital and analog sections, each with its own ground. The plot should be placed on a split plane that separates the routing and power planes. The 4DF1706 and all digital circuits should be placed in the digital section, while the audio D/A converter(s) and analog circuits should be placed over the analog section of the board. The common reason for the connection between digital and analog is that it is necessary to do it at a single point, as shown.

For Figure 4(a), the digital signal should be routed from the DF1706 to the audio D/A using a short direct converter(S) connection to reduce the amount of radiated high frequency Quincy energy. If desired, series resistors can be placed in the clock and data signal paths to reduce or eliminate any overshoot or undershoot present on these signals. A value of 50Ω to 100Ω is recommended as a starting point, but designers should experiment with resistor values for best results. Figure 4(b) shows an improved method, high-mans, mixed-signal board layout. This method combines the digital isolation of the DF1706 and the audio D/A converter(s) and provides complete isolation between the digital and analog portions of the board. The ISO150 dual digital couplers provide excellent isolation and operate at speeds up to 80Mbps.

Figure 4

Power and Bypass

The DF1706 needs to operate from a single +5V power supply. The supply should be bypassed by a 10µF, 0.1µF capacitor in parallel. The capacitor should be placed as close as possible to VDD (pin 22). Aluminum electrolytic or tantalum capacitors are available for 10µF values, while ceramics are available for 0.1µF values.

basic circuit connections

Figures 5 and 6 are the basic circuit connections for the DF1706. Figure 5 shows the connection control for the device mode, while the software is used for the connection mode control as shown in Figure 6. Note that C1 and C2 are placed in both figures because they are physically close to the DF1706.

Figure 5

Image 6