The AD9059 is a dual 8-bit monolithic analog-to-digital converter optimized for low cost, low power consumption, small size and ease of use. With a 60 MSPS code rate and full power analog with a typical bandwidth of 120 MHz, this component is ideal for applications requiring multiple ADCs with excellent dynamic performance.

To minimize system cost and power consumption, the AD9059 includes an internal 2.5 V reference and dual keeper circuitry. The ADC only needs 5 V supply and an encoding clock. There are no external references or driver components required by many applications.

The single encoded input of the AD9059 is TTL/CMOS compatible and controls two internal ADC channels simultaneously. This parallel 8-bit digital output operates at 5 V or 3 V consumables. The total power consumption is <12 mW for long periods of time when the power down function is not required and the ADC data is not required. In power save mode, the digitized outputs are driven to a high impedance state.

Manufactured on an advanced BiCMOS process, the AD9059 is available in a space saving 28-lead shrink small outline package (28-lead SSOP) and is industrially specified over the temperature range (-40°C to +85°C). Customers who want single-channel digitization can consider using

AD9057, based on a single 8-bit, 60 MSPS microcontroller AD9059 ADC core. The AD9057 is available in a 20-lead Shrink Small Outline Package (20-lead SSOP) and is specified over the industrial temperature range.

feature

Dual 8-bit ADCs on a single chip

Low power: 400 mW typical

On-chip 2.5 V reference and track-and-hold

1 V pp analog input range

Single 5V Supply Operation

5 V or 3 V logic interface

120 MHz analog bandwidth

Power-down mode: <12 mW

application

Digital Communications (QAM Demodulator)

RGB and YC/composite video processing

Digital data storage read channel

Medical Imaging

digital meter

Functional block diagram

PIN configuration diagram

Theory of Operation

The AD9059 combines ADI's proprietary MagAmp gray-code conversion circuit with flash converter technology to provide dual high-performance 8-bit ADCs in a single-chip device at low cost. The design architecture ensures low power consumption, high speed, and 8-bit precision.

The AD9059 provides two clocked linked ADC channels from a single ENCODE input (see functional block diagram). Two ADC channels simultaneously sample analog inputs (AINA and AINB) and provide non-interleaved parallel digital

Output (D0A-D7A and D0B-D7B). The voltage reference (VREF) is connected internally to both ADCs, so the channel gain and offset will track whether external reference control is required. The analog input signal is channel buffered at the input of each ADC and used for high-speed track and hold. The track and hold circuit maintains the analog input value conversion process during the hold period (starting from the rising edge of the ENCODE command). The track-and-hold output signal is passed through Gray code and flash conversion stages to generate coarse and fine digital representations of the held analog input levels. The decode logic combines multiple levels of data and aligns the strobe output on the rising edge of ENCODE into an 8-bit word command. The MagAmp/Flash architecture of the AD9059 results in three pipeline delays for the output data. Using AD9059

Analog Inputs The AD9059 provides independent single-ended high impedance (150kΩ) analog inputs for dual ADCs. Each input requires a DC bias current of 6µA (typ) centered near 2.5 V (±10%). This DC offset can be provided by the user, or it can be derived from the ADC's internal reference voltage. The figure below shows that low-cost DC allows the user to capacitively couple the bias to enable the AC signal to go directly to the ADC without the need for additional active circuitry. For best dynamic performance, the VREF pin should be decoupled to ground with a 0.1µF capacitor (to minimize the modulation reference voltage), and the bias resistor should be about 1kΩ.

Capacitively coupled AD9059

The figure below shows a typical connection for high performance DC biased using the ADC's internal voltage reference. All components can be powered from a single 5V supply (analog input signals are ground referenced).

DC Coupled AD9059 (VIN Inverted)

voltage reference

Built-in stable, accurate 2.5 V reference AD9059 (VREF). The reference output is used to set the ADC gain/offset and provides a DC offset for the analog input signal. The internal reference is connected to the ADC circuit through an 800 Ω internal impedance, capable of supplying 300 μA of external drive current (for DC bias analog input or other user circuits). Certain applications may require higher quasi-temperature performance, or gain adjustments that cannot be made using an internal reference. An external voltage may be applied to the VREF pin to overdrive the internal voltage gain adjustment reference by up to ±10% (the VREF pin is directly connected internally to the ADC circuit). The ADC gain and offset will be varied simultaneously with the external reference adjustment in a 1:1 ratio (2% or 50 mV adjustment to 2.5 V reference increases ADC gain by 2% and ADC offset by 50 mV).

Digital logic (5 V/3 V system)

The digital inputs and outputs of the AD9059 can be easily configured to interface directly with 3 V or 5 V logic systems. The Code and Power Down (PWRDN) input is a CMOS TTL threshold of 1.5 V stage, making the input compatible with TTL, 5 V CMOS and 3 V CMOS logic families. As with all high-speed data converters, the encoded signal should be clean and dithered to prevent the ADC from dynamically degrading performance.

The digital outputs of the AD9059 can also interface directly with 5 V or 3 V CMOS logic systems. The power supply pin (VDD) is used to supply these CMOS stages isolated from the analog VD voltage. By changing the voltage on these supply pins, the digitized output high level will change for a 5 V or 3 V system. The VDD pin is internally connected on the AD9059 chip. Care should be taken to isolate the 5V supply voltage and the 5V analog voltage supply to minimize noise coupled to the ADC.

The AD9059 provides high impedance digital output operation when the ADC enters power-down mode (PWRDN, logic high). A 200 ns (minimum) power down time should be provided before the high impedance characteristic is required. One provides a 200 ns power-up time to ensure accurate reactivation of ADC output data (valid output data is available within three clock cycles after a 200 ns delay). The timing AD9059 is guaranteed to operate at conversion rates from 5 MSPS to 60 MSPS. At 60 MSPS, the ADC is carefully designed to operate with a 50% code duty cycle, but the performance is insensitive to moderate changes. A pulse width variation of ±10% (allowing the encoded signal to meet the min/max high/low specifications) will not degrade ADC performance. The AD9059 cannot operate in binaural ping-pong mode due to the interconnected ENCODE architecture of the ADCs. Power consumption The power consumption of the AD9059 is specified to reflect a typical application setting under the following conditions: Coded at 60 MSPS, analog input is -0.5 dBFS at 10.3 MHz, VD is 5 V, VDD is 3 V, digital output typical 7 pF (up to 10 pF). Actual dissipation therefore varies by modifying conditions in the user application. TPC 7 shows the typical power consumption frequency and VDD supply voltage for the AD9059 and ADC encoding. A power saving feature allows the user to reduce power consumption when ADC data is not needed. The TTL/CMOS high signal (PWRDN) turns off the part of the dual ADC and brings the total power consumption to less than 10 mW. The internal bandgap supply reference remains active in power-down mode to minimize ADC reactivation time. If the power-down function is not desired, pin 3 should be grounded. Both ADC channels are controlled simultaneously by the PWRDN pin; they cannot be turned off or turned on independently.

application

The wide analog bandwidth of the AD9059 makes it attractive for a variety of high performance receiver and encoder applications. The figure below shows a typical low-cost I and Q dual ADC wired, satellite or wireless demodulator implementing a LAN modem receiver. Excellent dynamic performance ADC with high analog input frequency and code rate enables users to use direct IF sampling techniques. IF sampling eliminates or simplifies the analog mixer and filtering stages to reduce overall system cost and power.

The high sample rate and analog bandwidth of the AD9059 are ideal for computer RGB video digitizer applications. With a full-power analog bandwidth of twice the maximum sample rate, the ADC provides sufficient pixel-to-pixel transient settling time to ensure accurate 60 MSPS video digitization. The figure below shows a typical RGB video digitizer implementation of the AD9059.

The AD9059/PCB evaluation board is an easy-to-use analog/digital interface for a dual, 8-bit, 60 MSPS ADC. The board includes various high-level typical hardware configurations to accelerate digital evaluation. On-board components include the AD9059 (in a 28-pin SSOP package), optional analog input buffer amplifier, digital output latches, board timing drivers, and configurable jumpers for AC-coupled, DC-coupled, and power-down functional testing. The board is factory configured to use the AD9059's internal reference voltage for DC coupling. For DC-coupled analog input applications, amplifiers U3 and U4 are configured as an adjustable unity gain inverter analog input signal offset. For full-scale ADC driving, each analog input signal should be 1 V pp, referenced 50Ω to ground. Each amplifier offsets its analog signal by +VREF (2.5 V typical) to center the voltage for proper ADC input drive. For DC-coupled operation, connect E7 to E9 (analog input A to R11 ), E14 to E13 (amp output to analog input A of AD9059), E4 to E5 (analog input B to R10) and E11 to E10 (using the board Connect the amplifier output to the AD9059's analog input B) Jumper connector. For AC-coupled analog input applications, amplifiers U3 and U4 are removed from the analog signal path. The analog signals are coupled through capacitors C11 and C12, each terminated with a VREF voltage (providing bias current for the AD9059 analog inputs, AINA and AINB) through separate 1kΩ resistors.

The analog input signal to the board should be 1 V pp into 50Ω for full-scale ADC drive. For AC-coupled operation, connect E7 to E8 (analog input A to C12 shoot-through capacitor), E13 to E15 (C12 to R15 termination resistor for channel A), E4 to E6 (analog input B to C11 shoot-through capacitor) and E10 to E12 (C11 to R14 terminating resistor for channel B) uses a board jumper connector. The on-board voltage reference can be used to drive the ADC or an external reference can be applied. The standard configuration uses an internal voltage reference without any external voltage connection requirements. The external reference voltage can be a current output applied to the board connector input REF to overload limit the internal reference voltage of the AD9059. This external reference voltage should be 2.5 V typical. It can be connected via board jumpers using the power-down feature of the AD9059. Connect E2 to E1 (5 V to PWRDN) for power-down mode operation. For normal operation, connect E3 to E1 (ground to PWRDN).

The encoded signal source should be TTL/CMOS compatible and capable of driving 50Ω terminations. Digital Output In evaluation, the AD9059 is buffered by latches (U5 and U6), available to the user of the connector using pins 30-37 and pins 22-29. The latch timing is derived from providing the ADC ENCODE clock and digital clock signals to the board user at connector pins 2 and 21.