feature
Key features of the Z80180 Microprocessor Unit (MPU) include:
• Code compatible with Zilog Z80 CPU®
• Extended instructions • Two DMA channels • Low power modes • On-chip interrupt controller • Three on-chip wait state generators • On-chip oscillator/generator • Extended MMU addressing (up to 1 MB)
• Clocked serial I/O port • Two 16-bit counters/timers • Two UARTs
• Clock speed: 6 MHz, 8 MHz and 10 MHz • 6 MHz version supports 6.144 MHz CPU clock operation • Operating range: 5 V
• Operating temperature range: 0°C to +70°C.
• Three package types 68-pin PLCC-
- 64-pin DIP 80-pin QFP
General Instructions
The Z80180 8482 ; is an 8-bit MPU that provides the benefit of reducing system cost and also provides full backward compatibility with existing Zilog Z80 devices.
System cost is reduced by combining several key system functions with the CPU. These key functions include I/O devices such as DMA, UART, and timer channels. Also included on the chip are wait state generators, clock oscillators and interrupt controllers.
The Z80180™ is packaged in 80-pin QFP, 68-pin PLCC and 64-pin DIP packages.
NOTE: All signals with an upper bar are active low signals. For example, b/w, where word is active low); b/w, where byte is active low.

Pin description
A0— A19 . Address Bus (Output, Active High, 3-State) A – Forms a 20-bit address bus. The address bus provides addresses for memory data bus exchanges, up to 1 MB, and the I/O data bus exchanges provide addresses, up to 64 KB. The address bus goes into a high impedance state during reset and external bus acknowledgement cycles. Address line A18 is multiplexed with the output of Programmable Reload Timer (PRT) channel 1 (T, selected as address output on reset), address line A19 is not available in the DIP version of the Z80180. 019 out
BasACK bus acknowledgment (output, active low). Busack represents the requesting device, the MPU address and data bus, and some control signals that go into a high-impedance state.
Blake bus request (input, active low). External devices such as DMA controllers use this input to request access to the system bus. This request requires higher priority than NMI and is always recognized at the end of the current machine cycle. This signal prevents the CPU from executing further instructions and places the address and data buses and other control signals in a high impedance state.
CKA0, CKA1 - Asynchronous clocks 0 and 1 (bidirectional, active high). When in output mode, these pins are the transmit and receive clocks.
Output from ASCI Baud Rate Generator. In input mode, these pins are used as external clock inputs for the ASCI baud rate generator. CKA0 is multiplexed with DREQ0,
CKA1 is multiplexed with TEND0.
CKS - Serial Clock (bidirectional, active high). This line is the clock for the CSIO channel.
clock - system clock (output, active high). The output is used as a reference clock for the MPU and external systems. The frequency of this output is equal to half the frequency of the crystal or input clock.
CTS0 - CTS1 - Clear to send 0s and 1s (input, active low). These lines are the modem control signals for the ASCI channel. CTS1 is multiplexed with RXS.
D0- D7- Data bus (bidirectional, high level, 3-state). D0–D7 form an 8-bit bidirectional data bus for transferring information between input/output and storage devices. During reset and external bus acknowledgement cycles, the data bus goes into a high impedance state.
DCD0 - Data carrier detection 0 (input, active low). Programmable modem control signal for ASCI channel 0.
DRYQ0, DRYQ1. DMA requests 0 and 1 (input, active low). DREQ is used to request a DMA transfer from one of the DMA channels on the chip. The DMA channel monitors these inputs to determine when the external device is ready for a read or write operation. These inputs can be programmed for level or edge sensing. DREQ0 is multiplexed with CKA0.
E - Enable clock (output, active high). Synchronous machine cycle clock output during bus transactions.
External - External clock crystal (input, active high). Crystal oscillator connection. When not using a crystal, an external clock can be input to the Z80180 on this pin. This input is Schmitt-triggered.
stop - stop/sleep (output, active low). This output is asserted after the CPU executes a halt or sleep instruction and waits for an interrupt before non-maskable or maskable operation resumes. It is also used in conjunction with the M1 and ST signals to decode the state of the CPU machine cycle.
Intel 0 - Maskable interrupt request 0 (input, active low). This signal is generated by an external I/O device. The CPU treats these requests as long as the NMI and BUSREQ signals are inactive at the end of the current instruction cycle. The CPU acknowledges this interrupt request acknowledgement cycle with an interrupt. During this cycle, both the M1 and IORQ signals become active.
It1, Int - Maskable interrupt request 1 and 2 (input, active low). This signal is generated by an external I/O device. The CPU fulfills these requests at the end of the current instruction cycle as long as the NMI, Blake and Intel 0 signals are deasserted. The CPU acknowledges these requests through interrupt acknowledgement cycles. Unlike Intel 0, the M1 or IORQ signal is active in this cycle.
IORQI/O request (output, active low, 3-state). IORQ means address bus connection -
Provides a valid I/O address for I/O read and write operations. also generates an IORQ,
Together with M1, during the acknowledgment of the INT0 input signal, indicating -
Interrupt response vectors can be placed on the data bus. This signal is similar to the IOE signal of the Z64180.
M1 - Machine cycle 1 (output, active low). Together with MReq, M1 indicates that the current loop is an opcode fetch loop and instruction execution. Together with IORQ, M1 indicates the current cycle for interrupt acknowledgement. It is also used for stall and load order signals to decode the CPU machine cycle status. This signal is similar to that of the lidar Z64180.
MREQ - Memory Request (output, active low, 3-state). MREQ indicates that the address bus reserves effective addresses for memory read and write operations. This signal is similar to the ME signal of the Z64180.
NMI - Non-Maskable Interrupt (input, triggers negative edge). The NMI requirement is more than international and is always recognized at the end of the instruction, regardless of the state of the interrupt enable flip-flop. This signal forces the CPU to continue execution at position for 0.66 h.
RD - opcode reinitialization (output, active low, 3-state). rd indicates that the CPU wants to read data from memory or an I/O device. Addressing I/O or memory devices must use this signal to strobe data onto the CPU data bus.
RSF - Refresh (output, active low). Together with mreq, rfsh indicates that the current CPU machine cycle and the contents of the address bus must be used for the refresh of dynamic memory. The lower 8 bits of the address bus (A7–A10) contain the refresh address.
This signal is similar to the reference signal of the Z64180.
RTS0 - Request to send 0 (output, active low). Programmable modem control signal for ASCI channel 0.
RXA0, RXA1 - Receive data 0 and 1 (input, active high). These signals are the received data to the ASCI channel.
RXS - Clock serial receive data (input, active high). This line is the receiver data for the CSIO channel. RXS is multiplexed with CTS1 signal of ASCI channel 1.
St - state (output, active high). This signal is used with the M1 and HALT outputs to decode the state of the CPU machine cycle.

notes:
X = reserved.
mc=machine cycle.

Tendon 1 transmits terminals 0 and 1 (output, active low). During the most recent write cycle of the DMA, this output is asserted as the active output.
operate. It is used to indicate the end of a block transfer. tend0 with
CKA1
test - test (output, not DIP version). This pin is used for testing and must be left open.
brag - timeout(output, active high). T is the pulse output from PRT channel 1. This line is multiplexed with A18 of the address bus. out
TXA0, TXA1 - transmit data 0 and 1 (output, active high). These signals are the transmitted data from the ASCI channel. The change of the transmission data is related to the falling edge of the transmission clock.
TX--Clock transmits data serially (output, active high). This line is the data transmitted from the CSIO channel.
wait - wait(input, active low). Waiting to indicate the address memory to the MPU or
The I/O device is not ready for data transfer. This input is sampled on the falling edge of t2 (and subsequent wait states). If the input sample rate is low, the additional wait state is inserted until the pending input is sampled high, at which point execution continues.
WR - Write (output, active low, 3-state). wr means that the CPU data bus stores valid data at an address I/O or memory location.
XTAL crystal (input, active high). Crystal oscillator connection. If using an external clock instead of a crystal, you must keep this pin open. The oscillator input is not TTL level (see DC Characteristics on page 21). There are several pins for different situations, depending on the situation.
Multiplexed Pin Descriptions Multiplexed Pin Descriptions Pin Descriptions
A18/T is out During the reset process, this pin is initialized as A18 pin. The T function is selected if the TOC1 or TOC0 bit of the Timer Control Register (TCR) is set to 1. If TOC1 and TOC0 are cleared to 0, the A18 function is selected. out
CKA0/DRYQ0
During reset, this pin is initialized as the CKA0 pin. If dm1 or sm1 in the dma mode register (dmode) is set to 1, the dreq0 function is always selected.
CKA1/RAND0
During reset, this pin is initialized as the CKA1 pin. The tend0 function is selected if the cka1d bit in the asci control register ch1 (cntla1) is set to 1. If the CKA1D bit is set to 0, the CKA1 function is selected.
RXS/CTS1
During reset, this pin is initialized as the RXS pin. The cts1 function is selected if the cts1e bit in the asci status register ch1 (stat1) is set to 1. If the CTS1E bit is set to 0, the RXS function is selected.
architecture
The Z180 combines high-performance CPU cores with a variety of ®
System and I/O resources are useful in a wide range of applications. The CPU core consists of five functional blocks: clock generator, bus state controller, interrupt controller, memory management unit (MMU) and central processing unit (CPU). Integrated I/O resources make up the remaining four functional blocks: Direct Memory Access (DMA) control (2 channels), Asynchronous Serial Communication Interface (ASCI) 2 channels, Programmable Reload Timer (PRT) 2 channels and clock serial I/O (CSIO) channels.
Clock Generator - Generate system clock from external crystal or clock input. External clocks are divided into two or one and are provided to internal and external devices.
Bus Status Controller - This logic performs all status and bus control activities related to the CPU and some on-chip peripherals. Includes wait state timing, reset cycles, DRAM refreshes, and DMA bus swaps.
Interrupt Controller - This logic monitors and prioritizes various internal and external interrupts and traps to provide proper responses from the CPU. To maintain compatibility with Z80 CPUs, three different interrupt modes are supported. ®
Memory Management Unit - MMU allows you to map the memory used by the CPU (logically only 64 KB) into the 1-MB addressing range supported by the z80180. The organization of the MMU object code allows maintaining compatibility with the Z80 CPU while providing access to the extended memory space. The organization is achieved through the use of an effective public area banking regional scheme.
Central Processing Unit - The CPU is microcoded to provide an object code core compatible with the Z80 CPU. It also provides a superset of the Z80 instruction set, including 8-bit multiplication. The core was modified to allow many instructions to execute in fewer clock cycles.
DMA Controller - The DMA controller provides high-speed transfers between memory and I/O devices. Supported transfer operations are memory to memory, memory to/from I/O, and I/O to I/O. The supported transfer modes are Request, Burst, and Cycle Steal. DMA transfers can access the full 1 MB address range, block lengths up to 64 KB, and can span 64K boundaries.
Asynchronous Serial Communication Interface ASCI Logic provides two separate full-duplex UARTs. Each channel includes a programmable baud rate generator and modem control signals. ASCI channels also support multiprocessor communication formats and interrupt detection and generation.
Programmable Reload Timer (PRT) This logic consists of two independent channels, each containing a 16-bit counter (timer) and count reload register. The time base of the counter is derived from the system clock (divided by 20) before reaching the counter. PRT channel 1 provides an optional output to allow waveform generation.
Timer Data Register

Timer Data Register Clock Serial I/O (CSIO). The CSIO channel provides a half-duplex serial transmitter and receiver. This channel can be used for simple high-speed data connections to other microprocessors or microcomputers. TRDR is used for CSIO transmission and reception. The system design must ensure that the constraints for half-duplex operation are met. Send and receive operations cannot occur at the same time. For example, if CSIO transmission is attempted while CSIO is receiving data, CSIO does not work.
Note: Relay forwarding is not buffered. An attempt is being made to execute a CIO transfer while the previous transfer data is still being shifted out, causing the shift data to update immediately, disrupting the ongoing transfer operation. Reading trdr during transmission or reception must be avoided.
CSIO Block Diagram Operation Modes
Z80 Compatible with 64180®
The Z80180 is the descendant of two different ancestor processors, Zilog's original Z80 and the Hitachi 64180. Operation Mode Control Register (OMCR), programmable to select between certain Z80 and 64180 differences.
- Operation Control Register (OMCR: I/O Address = 3eh)
M1E (M1 Enable) - This bit controls the M1 output and is set to 1 during reset.
When m1e = 1, the m1 output is asserted low during the opcode fetch loop, the int0 acknowledgement loop, and the first machine cycle of the NMI acknowledgement.
On the Z80180, this option allows the processor to fetch the RETI instruction only once, using three clock machine cycles when fetching RETI from zero-wait-state memory, which is not fully Z80 timing compatible, but is compatible with the on-chip CTC.
When m1e=0, the processor does not drive m1 low during instruction fetch cycles. Under normal timing, after fetching the RETI instruction only once, the processor returns and re-etches the instruction using a fully Z80-compatible loop that includes driving M1 low. Some external Z80 peripherals may require properly decoded RETI instructions. Figure 9 illustrates the reti sequence when m1e=0.
RETI instruction sequence with MIE=0
M1TE (M1 Temporary Enable) - This bit controls the temporary
Assertion of the M1 signal. It is always read as 1 and set to 1 during reset.
When m1e is set to 0 to accommodate some external z80 peripherals, these same devices may need to pulse on m1 after programming some of its registers to complete the function being programmed.
For example, when the control word is written to the Z80 PIO to enable interrupts, the de-enable actually happens before the PIO recognizes the active M1 signal. When m1te=1, no
The operation of the M1 signal changes and the M1E controls its function. When m1te=0, the m1 output is asserted on the next opcode fetch cycle, regardless of the state programmed into the M1E bit. This instance is only temporary (once only) and does not need to be pre-programmed with 1 to disable the function (see Figure 10).
M1 Temporary Enable Time IOC This bit controls the timing of the IORQ and RD signals. Set it to 1 by reset. when?
I/O read and write cycle of IOC=1 When IOC=0, the time of IORQ and RD signal matches the time of Z80. Due to the rising edge of t2, the IORQ and RD signals become active (see Figure 12).
I/O read and write cycle shutdown and low power operating modes with IOC=0 - the Z80180 can operate in five modes including active and power consumption:
• Normal operation • Stop mode • iostop mode • Sleep mode • System stop mode Normal operation - The Z80180 processor is fetching and running a program. All enabled device features and parts are active and the stop pin is high.
Stop Mode This mode is entered by the HALT instruction. After this, the Z80180 processor continues to fetch the following opcode, but does not execute it, and drives stop with both ST and M1 pins low. Oscillator and power factor pins remain active, interrupts and buses are granted to external masters, DRAM refreshes may occur, and all on-chip I/O devices continue to operate, including DMA channels.
The Z80180 leaves stop mode in response to a low-on reset, an external request from an enabled on-chip source, an external request on NMI, or an enabled external request on INT0,
It1 or It2. In the case of an interrupt, the return address is the instruction following the HALT instruction; at this point, the program can branch back to the HALT instruction to wait for another interrupt, or it can check for the new state of the system/application and respond appropriately.
Suspend the timing sleep mode by setting the 3rd and 6th bits of the iostop bit (ICR5) of the CPU control register (CCR3, CCR6) to zero and executing the sleep instruction to enter the sleep mode. Oscillator and power factor outputs continue to work, but are blocked from CPU cores and DMA channels to reduce power consumption. DRAM refresh is stopped, but an interrupt may occur and be granted to an external host. Unless the bus is granted to an external master,
A19–0 and all control signals except shutdown are held high. Stop is Low. Except for the DMA channel, I/O operations continue as before the sleep instruction.
The Z80180 leaves sleep mode in response to a boot-low reset and an interrupt request from an on-chip source, an external request from the NMI, or an external request on int0, int1, or int2.
If an interrupt source is disabled individually, it cannot bring the Z80180 out of sleep mode. If an interrupt source is individually enabled, and the ief bit is 1, so the interrupt is globally enabled (by the ei instruction), the highest priority active interrupt occurs, and the return address is the instruction following the sleep instruction. If the interrupt sources are individually enabled, but the ief bit is 0, so interrupts are disabled globally (via the DI instruction), the z80180 simply executes the following instruction to exit sleep mode.
This provides a technique for synchronizing to high-speed external events without incurring the delays imposed by interrupt response sequences. Time to exit sleep mode due to interrupt request.
NOTE: The Z80180 takes about 1.5 clocks to restart.
Sleep Time Stop Mode is entered by setting the iostop bit in the I/O Control Register (ICR) to 1. In this case, the on-chip I/O (asci, csio, prt) stops working. However, the CPU continues to work. Recovery from iostop mode is done by resetting the iostop bit in the icr to 0
System Stop Mode - System stop mode is a combination of sleep and iostop modes. System stop mode is entered by setting the iostop bit in the ICR to 1 and then executing the sleep instruction. In this mode, the on-chip I/O and CPU stop working, reducing power consumption, but the power factor output continues to work. Resuming from system stop mode is the same as resuming from sleep mode, except that internal I/O sources (disabled by io stop) cannot generate resume interrupts.
Standard Test Conditions The DC Characteristics section applies to the following Standard Test Conditions unless otherwise stated. All voltages are referenced to GND (0 V). Positive current flows into the reference pin.
All AC parameters assume a load capacitance of 100 pF. For every 50 pf load, add 10 ns of latency, up to 200 pf for the data bus and 100 pf for the address and control lines. AC timing measurements are referenced to 1.5 volts (except the clock, which is referenced to the 10% and 90% points).