The N5396QI is a power-on-chip (PwrSoC) DC-DC converter. It is specifically designed to meet the precise voltage and fast current and future transient requirements of high-performance, low-power processors, DSPs, FPGAs, ASICs, memory boards and system-level applications in distributed power architectures. Advanced circuit technology, ultra-high conversion frequencies, and innovative, high-density, integrated circuit and dedicated inductor technologies provide high-quality, ultra-compact, non-isolated DC-DC conversion. This converter requires the first five external components, including small value input and output ceramic capacitors and soft-start capacitors.

Typical application circuit:

Selection of Input Capacitors

The EN5396QI requires about 100uF of input capacitance. Low ESR ceramic capacitors need to be formulated with an X5R or X7R dielectric rating. Y5V or equivalent dielectric constant formulations cannot be used because these transmission capacitances vary with frequency, temperature and bias voltage. In some applications, lower value capacitors are required in parallel with larger, capacitors in order to provide high frequency decoupling.

enable action

The enable pin provides a means to shut down the device, or to operate normally. The logic will disable the converter and turn it off. A logic high will transition the converter to normal operation. When the enable pin is set high, the device will undergo a normal soft-start.

soft start operation

Soft start is such a method to reduce inrush current when the device is turned on. Starts when the output voltage is slowly rising. The output rise time is controlled by the selected soft-start capacitor, which is placed between the SS pin (Pin 48) and the AGND pin (Pin 40). Rise time: t R=Css*80K? During start-up of the converter, the reference voltage error amplifier is gradually raised from the internal current to its final level source typically 10uA. Typical soft-start rise times are 1ms to 3ms. Typical capacitance values for SS are in the range of 15nF to 30nF.

Pin Configuration:

POK operation

The POK signal is derived from an open-drain signal converter indicating that the output voltage is within the specified range. The POK signal will be a logic high when the output voltage is at 90%-120% of the programmed output voltage. If the output voltage goes outside this range, the POK signal will be a logic low until the output voltage returns within this range. In an overvoltage condition the POK event signal will go low and will remain in this state until the output voltage has dropped to 95% of the programmed output voltage before returning to the high state. The internal POK FET is designed to withstand up to 4mA. The pull-up resistor value should be chosen to limit the current to a logic low level when POK does not exceed this value.

overcurrent protection

When an overcurrent condition occurs, VOUTis is pulled low. This condition is maintained for a 1.2 ms, and then the normal soft-start cycle begins. If the overcurrent condition persists, the cycle will repeat. The OCP trigger point is nominally set to 150% of maximum rated load. It is therefore possible to increase the OCP trip point to a maximum of 200 % of the rated load by connecting a 5kΩ resistor between the ROCP pin (pin 38) and AGND (pin 39). This option is used to boot into capacitive loads such as some FPGAs and ASICs.

Over voltage protection

When the output voltage exceeds 120% of the programmed output voltage, the PWM operation is stopped, the low N-MOSFET is turned on and the POK signal goes low. When the output voltage falls below 95% of the programmed output voltage, normal PWM operation resumes and POK returns to the high state.

Thermal overload protection

A thermal shutdown feature will disable operation once the junction temperature exceeds approximately 150oC. When the junction temperature drops by about 20°C, the converter will resume a normal soft-start.

block diagram: