The CA3140A and CA3140 dual ICs operate a monolithic microcontroller with high voltage transistors on PMOS transistors that combine the advantages of high voltage amplifiers.

The CA3140A and CA3140 BiMOS op amps feature gate-protected MOSFET (PMOS) transistor input circuits that provide very high input impedance, very low input current, and high-speed performance. The CA3140A and CA3140 operate on supply voltages from 4V to 36V (single or dual supply). These op amps are internally phase compensated for stable unity-gain follower operation, and additionally have access terminals for auxiliary external capacitors if additional frequency roll-off is required. Termination is also provided for applications that require input offset voltage nulling. The use of PMOS field effect transistors at the input stage causes the common-mode input voltage capability to drop below 0.5V on the negative supply side, an important property for single-supply applications. Bipolar transistors are used in the output stage, with built-in protection against damage caused by short-circuiting the load terminals to the supply rail or ground.

The CA3140A and CA3140 are suitable for supply voltages up to 36V ( 18V ).

feature

MOSFET Input Stage - Very High Input Impedance (ZIN) -1.5T (typ) - Very Low Input Current (Il) -10pA (typ) at p15V - Wide Common Mode Input Voltage Range (VlCR) - Can Swing 0.5V- Output Swing Complement Input Common Mode Below Negative Supply Rail.

scope

Drop-in replacement for Type 741 Industrial in most applications

Lead-free plus annealing available (RoHS compliant)

application

Ground Referenced Single Supply Amplifier for Automotive and Portable Instrumentation

Sample and Hold Amplifier

Long Duration Timer/Multivibrator (seconds minutes, hours)

Photocurrent meter

Peak detector

Active filter

Comparators

5V TTL systems and other low voltage interface supply voltage systems

All standard op amp applications

function generator

Tone Control

power supply

Portable Instruments

Intrusion Alarm System

CA3140 pin diagram

As shown in the block diagram below, the input terminal can be low voltage 0.5V below the negative rail. Two Class A amplifier stages provide voltage gain, and are unique to Class AB amplifier stages that provide the necessary current gain to drive low impedance loads. A bias circuit provides a cascaded constant current flow loop that controls the first and second stages. The CA3140 includes on-chip phase compensation capacitors sufficient for the required unity-gain voltage follower configuration. The input stage schematic consists of a differential input stage with PMOS field effect transistors (Q9, Q10) operating in mirrored pairs and bipolar transistors (Q11, Q12) used as load resistors along with resistors R2 to R5. The mirror pair transistor can also be used as a differential-to-single-ended converter to drive the base current to the second-stage bipolar transistor (Q13).

If desired, offset nulling can be achieved with a 10k potentiometer connected to terminals 1 and 5 and its slider arm to terminal 4. The cascode is connected to bipolar transistors Q2, Q5 are constant current sources for the input stage. The base bias circuit of the constant current source is described later. Small diodes D3, D4, D5 provide gate oxide protection from high voltage transients such as electrostatic power. second stage

Most of the voltage gain of the CA3140 is provided by the power supply to the second amplifier stage, provided by bipolar transistor Q13 and its cascode connected load resistors by bipolar transistors Q3, Q4. On-chip phase compensation, sufficient for most applications, is provided by C1. Additional Miller effect compensation (roll-off) can be done, if needed, simply by connecting a small capacitor between terminals 1 and 8. Terminal 8 is also used for the strobe output.

schematic, schematic

The CA3140 series circuits employ a broadband output stage that can sink the load to the negative supply to complement the negative supply PMOS input stage's ability to operate when close to the negative rail. The quiescent current circuit (Q17, Q18) in the emitter follower cascade is established by transistors (Q14, Q15) The base current is "mirrored" to the portion of the current bias circuit that flows through diode D2. When the CA3140 is running output terminal 6 is sourcing current, transistor Q18 functions as an emitter follower supplying current from the V+ bus (terminal 7), through D7, R9 and R11 . Under these conditions, the potential of collector Q13 is high enough to allow the necessary flow of base current to emitter follower Q17, which in turn drives Q18.

When the CA3140 is running, output terminal 6 is the current sink to the V-bus and transistor Q16 is the current sink element. Transistor Q16 is mirrored with D6, R7 and current is fed through Q21, R12 and Q20. Transistor Q20, in turn, is biased by current through R13, Zener diode D8 and R14. This dynamic current sink is controlled by voltage level sensing. For purposes of explanation, it is assumed that output terminal 6 is statically established at the potential midpoint between V+ and the V- supply rail. When the output current sink mode is operating, the collector potential of transistor Q13 is driven down to its quiescent level, causing Q17, Q18 to reduce the output voltage at terminal 6, if desired. Therefore, the gate terminal transistor Q21 of the PMOS is shifted toward the V-bus, thereby reducing the channel resistance of Q21. Therefore, there is a gradual increase in the current increment through Q20, R12, Q21, D6, R7, and Q16 base. As a result, Q16 sinks current from terminal 6 in direct response to incremental changes in the output voltage caused by Q18. This sink current will flow regardless of the load; any overcurrent is provided internally by the emitter follower Q18. The output circuit is short-circuit protected by. Q19 is provided, driven by the high voltage drop to develop on R11 under output short-circuit conditions. Under these conditions, the collector of Q19 diverts current from Q4 to reduce the base current drive from Q17, thereby limiting current flow at Q18 to the shorted load terminal. The quiescent current of all stages of the bias circuit (except the dynamic current sink) CA3140 depends on the bias current in R1. The function of this bias circuit is to establish and maintain constant current flow through D1, Q6, Q8 and D2. D1 is the junction of the diode-connected transistor mirror and the base-emitter in parallel with Q1, Q2, and Q3. D1 can be thought of as a current-sampling diode that senses the emitter currents of Q6 and Q6 and automatically adjusts the base current of Q6 (through Q1) to maintain a constant current through Q6, Q8, D2. The base current in Q2, Q3 is also determined by the constant current D1. Additionally, the current in diode-connected transistor Q2 builds up current in transistors Q14 and Q15.

typical application

The input and output characteristics with a wide dynamic range achieve the most ideal high input impedance characteristics. The unique design concept PMOS bipolar process is adopted in the CA3140. Input common-mode voltage range and output swing capability are complementary, allowing operation from a single supply voltage down to 4V. The wide dynamic range of these parameters also means that the device is suitable for many single-supply applications. For example, with one input driven below potential, phase detection of terminal 4 and the output signal must be maintained - the most important consideration in the comparison

application.