The DS1267 dual-channel digital potentiometer chip includes two digitally controlled, solid-state potentiometers. Each potentiometer consists of 256 resistor sections. The part between each resistor and the tap point at both ends of the potentiometer is the wiper that is accessed. The position of the wiper resistor on the array consists of an 8-bit value that controls which wiper point is connected to the wiper setting output. Communication and device control is accomplished through a 3-wire serial interface. This interface allows to be read or written at the device tap position. Two potentiometers can be connected in series (or stacked) for the same resolution as the added total resistance. For use in multi-device, single-processor environments, the DS1267 can be cascaded or daisy-chained. This feature provides control of multiple devices over a single three-wire bus. The DS1267 is available in three standard resistor values, including 10, 50, and 100 kOhm versions. Available software packages for the device include a 14-pin DIP, 16-pin SOIC package, and a 20-pin TSSOP package.

figure 1

The DS1267 contains two 256-bit potentials whose wiper position is set by an 8-bit value. These two 8-bit values are written to a 17-bit I/O shift register used to store the two wiper positions and stack select bits when the device is powered up. The block diagram of the DS1267 is presented in Figure 1. Communication and control in the DS1267 is accomplished through a 3-wire serial interface that drives an internal control logic unit. The 3-wire serial interface consists of three input signals: RST, CLK and DQ. The RST control signal is used to enable operation of the device's 3-wire serial port. The chip is selected when RST is high; RST must be high to initiate any communication to the DS1267. At the CLK signal input, it is used to provide input and output timing synchronization for data. The 17-bit I/O shift register of the DS1267 is used on the DQ signal line to transmit the potentiometer contact settings and stack select bit configuration. Figure 3(a) is a 3-wire serial interface protocol. As shown, the RST signal input is low when the 3-wire interface is inactive. Communication with the DS1267 requires a transition of RST from a low input state to a high state. Once the 3-wire port has been activated, data is input to the part on the low-to-high transition of the CLK signal input. The timing requirements for the three-wire serial timing provided are shown in the diagrams of Figure 3, (b)-(c). Data written to the DS1267 via the 3-wire serial interface is stored in a 17-bit I/O shift register (see Figure 2). The 17-bit I/O shift register contains the 8-bit potentiometer contact position value, stack select bits. In the I/O shift register composition, the I/O offset is presented at bit 0 in Figure 2. The register contains the stack select bit, which will be discussed in the section titled "StackedConfiguration." Bit 1 via I/O 8 of the O shift register contains the potential - 1 wiper position value. Bit 1 containing the MSB of the wiper setting is the wiper setting for potentiometer 1 and the LSB of bit 8. The 9 bits through the I/O shift register 16 contain the potential, the value of the 0 tap position, and the MSB tap position occupying the 9th bit and the LSB bit 16.

figure 2

The data transfer always starts with the stack select bit, followed by the potentiometer, the wiper 1 position value, and finally the potentiometer 0 wiper position value. When data at the tap position is to be written to the DS1267, 17 bits (or some integer multiple) of data should always be sent. Transactions that do not send the complete 17-bit (or more) will leave incomplete and possible registration errors in the desired tap position. After a communication transaction has completed, the RST signal input should take a low state to prevent any accidental changes to the device's shift register. Once RST has reached a low state, the contents of the I/O shift register are loaded into each multiplexer at the set tap position. The new wiper position will only be engaged after RST transitions to inactive. At device power-up the DS1267 wiper position will be set to 50% of the total resistance or binary value 1000 0000.

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