1. General Instructions
W681360 is a general-purpose single-channel 13-bit linear PCM codec with 2s complement data format. It is powered by a +3V supply and is available in 20-pin SOG (SOP), SSOP and TSSOP package options. The main function of this device is the digitization and reconstruction of speech signals, including band limiting and smoothing required for PCM systems. W681360 performance over the industrial temperature range -40°C to +85°C.
The W681360 includes an on-chip precision voltage reference. The analog part is fully differential to reduce noise and improve power supply rejection ratio. The VAG reference pin allows decoupling of internal circuits that generate a ground reference voltage to the VSS supply, minimizing clock noise on analog circuits when external analog signals are referenced to VSS.
The data transfer protocol supports long and short frames, synchronous and asynchronous communication for PCM applications. The W681360 accepts eight master clock rates between 256KHz and 4.800MHz, and the on-chip prescaler automatically determines the desired internal clock division ratio. An additional on-chip power amplifier can drive 300 Ω loads in various ways, up to 3.544V peak-to-peak.
For quick evaluation, a development kit (W681360DK) is available.
For rapid prototyping, a low-cost evaluation board (W681360ES) is also available.

2. Features •Single +3V supply (2.7V to 5.25V) Typical power consumption: 9.8mW Standby power consumption: 3µW
Power down power consumption: 0.09 microwatts • Low noise fully differential analog circuit design • 13-bit linear A/D&D/A conversion, 2s complement data format • Codec A/D and D/A filtering conforms to ITU G. 712
• 8 master clock frequencies from 256KHz to
4.800MHz 256KHz – 4.8MHz bit clock rate on serial PCM port On-chip accuracy reference of 0.886V for 600Ω (436mvrms) -5dBm TLP
• Programmable receive gain: 0 to –21db in
3dB steps • Industrial temperature range (–40°C to +85°C)
• 20-pin SOG (SOP), SSOP and TSSOP and QFN-32L packaging • Pb-free/RoHS packaging options available for applications • VoIP, voice network equipment • Digital telephone and communication systems • Wireless voice devices • DECT/digital cordless phones • Broadband connectivity Incoming devices • Bluetooth headsets • Fiber-to-the-curb devices • Business phones • Digital voice recorders

three. block diagram

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The first stage of the AD path of the W681360 Signal Path Transmit Path Codec is an analog input op amp with externally configurable gain settings. Differential analog inputs can be applied to inputs Ai+ and Ai-. Alternatively, the input amplifier can be powered down and a single-ended input signal can be applied to the AO pin or the AI pin. The input amplifier can be selected by connecting the AI+ pin to AO or AI+ as input. When the input op amp is powered down, the AO pin becomes high input impedance.
Input Amplifier When the input amplifier is powered down, the input signal at AO or AI- should be referenced to the analog ground voltage VAG.

The output of the input op amp is first fed through a low pass filter to prevent aliasing of the switched capacitor 3.4KHz low pass filter. Subsequently, the frequency band of the 3.4KHz switched capacitor low-pass filter limits the input signal below 4KHz. Signals above 4KHz will be aliased at a sample rate of 8KHz. A high-pass filter with a 200Hz cutoff frequency prevents DC coupling. All filters are designed according to the G.712 ITU-T specification. The high pass filter can be bypassed depending on the logic level on the HB pin. If the high pass is removed, the frequency response of the device extends down to DC.

After filtering, the signal is digitized into a 13-bit linear PCM code and fed to the PCM interface for serial transmission at the sampling rate provided by the external frame sync FST.
Input op amp gain The gain of the input op amp can be adjusted using external resistors. For single-ended input operation, the gain is given by a simple resistor ratio.
Input op amp gain - single-ended input

For differential input operation, the external resistor network is more complex, but the gain is expressed in the same way. Of course, differential inputs also have an inherent 6db advantage over their corresponding single-ended inputs.
Input op amp gain - differential input For microphone interface circuits, the gain of the op amp is typically set to 30dB. However, gain can be used above 30dB, but this will require a compact layout with minimal trace length and good noise source isolation. It is also recommended that the layout be as symmetrical as possible to prevent unbalanced operation from compromising the noise cancellation benefits of differential designs.
receive path
The 13-bit digital input samples of the d-to-a path are serially shifted in by the PCM interface and converted to parallel data bits. During each cycle of the frame sync FSR, parallel data bits are input through a 13-bit linear DAC and converted to analog samples. Analog samples are filtered through a low-pass smoothing filter with a 3.4KHz cutoff frequency according to the ITU-T G.712 specification. SIN(x)/x compensation is integrated with a low-pass smoothing filter. The output of the filter is buffered to provide the receive output signal ro-. The output can also be attenuated when the device is in receive path adjustment mode. If the device is half-channel operated with the FST pin clock and the FSR pin held low, the receive filter input will be tied to the VAG voltage. This minimizes transients at the Ro pin when resuming full channel operation by clocking the FSR pin.
The RO- output can be connected externally to the PAI pin to provide a differential output with high drive capability at the PAO+ and PAO- pins. Various gain settings for this output amplifier can be achieved by using external resistors. If the transmit power amplifier is not in use, it can be turned off by connecting PAI to VDD. The bias and signal reference for the PAO+ and PAO- outputs is the VAG pin. The VAG pins cannot source or sink current like these pins, so a low impedance load must be placed between PAO+ and PAO-. The PAO+ and PAO- differential drivers are also capable of driving 100Ω resistive loads or 100nF piezoelectric sensors in series with 20Ω resistors with slightly increased distortion. These drivers can be used to drive 32Ω resistive loads when the gain of the PAO- is set to 1/4 or less.
Receive gain adjustment mode
The W681360 can be put into receive path adjustment mode by applying a logic '1' to the BCLKR pin, while all other clocks are clocked normally. The device can then read 16 bits of data, and the other three coefficient bits are added to the 13 bits of digital speech data. These three coefficients are used to program the receive path attenuation, allowing the receive signal to be attenuated according to the values in the table below. If the feature is not used, the default value is 0db.

Attenuation factor relationship in receive gain adjustment mode Power management Analog and digital power
The power supply for the analog and digital parts of the W681360 must be 2.7V to 5.25V. This supply voltage is connected to the VDD pin. The VDD pin needs to be separated from ground by a 0.1µF ceramic capacitor. Analog Ground Reference Bypass This system features an internal precision voltage reference that generates a VDD/2 mid-supply analog ground voltage. This voltage needs to be decoupled from Vss at the Vref pin with a 0.1µf ceramic capacitor.
Analog Ground Reference Output An analog ground reference can be used as an external reference for the VAG pin. This voltage needs to be decoupled to Vss with a 0.01µF ceramic capacitor. The analog ground reference is generated from the voltage on the VREF pin and is also used for internal signal processing.
Pulse code modulation interface
The PCM interface is controlled by pins BCLKR, FSR, BCLKT and FST. Input data is received through the PCMR pin, and output data is transmitted through the PCMT pin.
Long frame sync or short frame sync interface mode can be selected by connecting the BCLKR or BCLKT pins to a 256KHz to 4.800 MHz clock, and connecting the FSR or FST pins to the 8KHz frame sync. The device synchronizes the data word of the PCM interface and the codec sample rate on the positive edge of the frame sync signal. Long frame sync is recognized when the fst pin is held high for two consecutive bit clock falling edges at the bclkt pin. The short frame sync mode is recognized when the frame sync signal of one and only one falling edge of the bit clock of the BCLKT pin is high at pin FST.
Long Frame Sync The device recognizes a long frame sync when the fst pin is held high for two consecutive bit clock falling edges at the bclkt pin. The length of the frame sync pulse can vary from frame to frame, as long as the positive sync edge of the frame occurs every 125µs. During data transmission in the long frame synchronization mode, when the frame synchronization signal fst is high or a 13-bit data word is transmitted, the transmission data pin pcmt will become low impedance. The transmit data pin pcmt will go high impedance when the frame sync signal fst goes low when data is being transmitted or when half the LSB is being transmitted. The internal decision logic will determine whether the next frame sync is a long frame sync or a short frame sync based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will have high impedance for two frame sync cycles after each power down state. The long frame sync mode is shown in the figure below. More detailed timing information can be found in the Interface Timing section

Long Frame Sync PCM Mode Short Frame Sync
The W681360 operates in short frame sync mode when the frame sync signal at pin fst is up to one and only one falling edge of the BCLKT pin bit clock. On the next rising edge of the bit clock, the W681360 starts clocking data on the PCMT pin, which also changes from a high-impedance state to a low-impedance state. The data transfer pin PCMT will return to a high impedance state through the LSB. The short frame synchronization operation of the W681360 is based on a 13-bit data word. When data on the PCMR pin is received, the data is clocked on the first falling edge after the falling edge consistent with the frame sync signal. The internal decision logic will determine whether the next frame sync is a long frame sync or a short frame sync based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will have high impedance for two frame sync cycles after each power down state. The short frame sync mode is shown in the figure below. More detailed timing information can be found in the Interface Timing section.
Short frame sync (separate clocks for transmit and receive) Short frame sync PCM mode Special 16-bit receive mode Sign extension mode Timing sign bit extension mode is entered by applying a logic "0" to the BCLKR pin, while all other clocks are clocked normally. In standard 13-bit mode, the first bit is the sign bit. In this mode, the device transmits and receives 16-bit data with the sign bit extended to the first four data bits. The PCM timing for this mode is shown below.
PCB sign extension (bclkr=0)
Both transmit and receive use bclkt, the first four data bits are sign bits.
FST may occur at a different time than FSR.
Sign Extension Mode Receive Gain Adjustment Mode Timed Receive Path Adjustment Mode is entered by applying a logic '1' to the BCLKR pin while all other clocks are clocked normally. In this mode, the device receives 16-bit data, where the last three bits are coefficients used to program the above-mentioned receive gain adjustment attenuation. The PCM timing for this mode is shown below.
PCB receive gain adjustment (bclkr=1)
Both transmit and receive use BCLKT. FST may occur at a different time than FSR. The clock goes into bits 14, 15 and 16 of the PCMR for the attenuation control of the received analog output.
Receive Gain Adjustment Timing Mode System Timing system can work at 256KHz, 512KHz, 1536KHz, 1544KHz, 2048KHz, 2560KHz, 4096KHz and 4800KHz master clock frequencies. The system clock is provided through the master clock input MCLK, which can be derived from the bit clock if desired. An internal prescaler is used to generate fixed 256KHz and 8KHz sample clocks for the internal codec. The prescaler measures the master clock frequency and frame sync frequency and sets the division ratio accordingly. If both frame syncs are low for the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the W681360 will enter a low power standby mode. Another way to power down is to set the PUI pin low. When the system needs to be powered up again, the PUI pin needs to be set high and the transmit frame sync pulse needs to be present. Two transmission frame synchronization periods are required before pin PCMT becomes low impedance.
On-Chip Power Amplifiers On-chip power amplifiers are typically used to drive external speakers. The inverting input of the power amplifier is available at pin PAI. The non-inverted input is internally bound to the VAG. Inverting Output PAO – Used to provide a feedback signal to the PAI pin to set the gain of the power amplifier outputs (PAO+ and PAO-). These push-pull outputs are capable of driving 300Ω loads. Connecting PAI to VDD will shut down the power driver amplifier and the PAO+ and PAO– outputs will be high impedance.