Features Suitable for multiple output and/or high voltage output voltage converters up to 500 kHz operation Buck converter stage high voltage high current floating driver UC3827-1 current feed controller with overlapping push-pull driver conduction cycles UC3827-2 voltage feed Controller with non-overlapping push-pull driver conduction cycles Average current mode, peak current mode or voltage mode with input Buck voltage feedforward control Power stage Wide bandwidth, low offset, differential current sense amplifier Accurate short circuit current control

describe
The UC3827 family of controller devices provides an integrated control solution for cascaded buck push-pull converters. Known as current or voltage feedback push-pull converters, these converters are ideal for multiple output and/or high voltage output applications. In current-fed and voltage-fed modes, the push-pull switch is driven at 50% of the rated duty cycle and half the switching frequency of the push-pull stage. In current-fed mode, the two switches are driven with a specified overlapping period to prevent ringing and voltage stress on the device. In voltage feed mode, the two switches are driven with a defined switching interval to prevent the transformer from short-circuiting the storage capacitor and to prevent excessive current flow through the device.
The output voltage of the converter is regulated by pulse width modulation of the buck switch. The UC3827 contains complete protection and PWM control functions for a buck converter. Simple control of the floating switch is done by the floating drive circuit. The gate drive waveform is leveled to support input voltages up to 72 Vdc.
Block Diagram Description (continued)
The UC3827 can use input voltage feedforward technique or current mode control in traditional voltage mode control. Potential core saturation of push-pull transformers due to timing and component tolerance mismatches can be prevented using current-mode control. Average current mode control allows precise control of the inductor current to the input push-pull stage without the noise sensitivity associated with peak current mode control. The UC3827 average current mode loop can also be paralleled with the voltage regulation loop to help only in fault conditions.
Other important features of the UC3827 include bidirectional synchronization capability, user programmable overlap time (UC3827-1), user programmable gap time (UC3827-2), high bandwidth differential current sense amplifier and soft-start circuitry.

Circuit Block Description Pulse Width Modulation Oscillator The block diagram of the oscillator with external connections is shown in Equation 1. The resistor (RT) connected to pin RT sets the linear charge current. The 2.5V timing capacitor (CCT) is charged linearly by the charge current, forcing the OSC pin to charge up to the 3.4 V threshold. After this threshold is crossed, the RS flip-flop is set to drive CLKSYN high and RDEAD low, releasing CCT. CT continues to discharge until the 0.5 V threshold is reached and resets the RS flip-flop, which repeats the charge sequence

As shown in Figure 3, multiple oscillators are synchronized to the highest free-running frequency by placing a 100 pF capacitor in series with each clksyn pin and connecting the other sides of the capacitors together to form the clksyn bus. The clksyn bus is then pulled down to ground with about 10 kΩ. Referring to Figure 1, the synchronization threshold is 1.4 V. The oscillator clears any sync pulses that occur while OSC is below 2.5 V. This allows the cell to continue through current discharge and subsequent charging when discharged below 2.5 V. loop, regardless of whether other units on the clksyn bus are still synchronizing. This requires all free-running oscillators to be within 17% frequency to ensure synchronization.