The ADS830 is a pipelined, CMOS analog-to-digital (A/D) converter that operates from a single +5V supply. The converter provides excellent performance with single-ended inputs and can operate with differential inputs for added spurious performance. This high-performance converter includes an 8-bit quantizer, high-bandwidth track/hold, and a high-precision internal reference. It also allows users to disable internal references and utilize external references. This external reference option provides excellent gain and offset matching when used in multi-channel applications or applications where scaling is required for full DC.

The ADS830 uses digital error correction technology to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra headroom required for medical imaging, communications, video and test instrumentation.

The ADS830 has a maximum sampling frequency of 60MHz and a single-ended input range of 1.5V to 3.5V. The ADS830 is pin-compatible with the 8-bit, 80MHz ADS831 in an SSOP-20 package.

feature

High SNR: 49.5dB

Internal/External Reference Options

Single-ended or differential analog input

Programmable Input Range: 1Vp-p / 2Vp-p

Low power: 170mW

Low DNL: 0.2LSB

Single +5V Supply Operation

SSOP-20 Packaging

application

medical imaging

Video Digitization

communication

disk drive control

PIN configuration diagram

Timing diagram

The ADS830 is a high speed CMOS A/D converter using a pipelined converter architecture consisting of 6 internal stages. Each stage feeds its data to digital error correction logic ensuring excellent differential linearity with no missing codes at the 8-bit level. Output data becomes valid on the rising edge of the clock (see timing diagram). This pipelined architecture results in a data delay cycle of 4 clocks.

The analog inputs to the ADS830 are differential track and hold, see Figure 1 below. Differential topology with closely matched capacitors yields high levels of ac performance at very high sampling rates.

The ADS830 allows its analog inputs to be driven single-ended or differential. A typical configuration of the ADS830 for the single-ended mode of the input track and hold performs the single-ended to differential conversion of the analog input signal. Both inputs (IN, IN) need to be externally biased (+VS/2) with a common-mode voltage usually at mid-supply levels. The following application discussion focuses on a single configuration. In general, its implementation is easier to implement and the ADS830's rated specifications are characterized using the single-ended mode of operation. Driving the analog input ADS830 enables excellent ac performance in single-ended or differential modes of operation. Choosing the best interface configuration depends on individual application requirements and institutional structure. For example, communications applications often deal with frequency ranges that do not include DC, while imaging applications, previously restored DC levels must

properly maintained to A/D converters. Features like the ADS830 input range selection (RSEL pin) or external reference options provide the flexibility needed to suit a variety of applications. In any of these cases, the ADS830 should be configured to meet the requirements of the application target driver amplifier when looking at headroom to yield the best overall performance.

INPUT CONFIGURATION AC-COUPLED SINGLE SUPPLY INTERFACE Figure 2 below shows a typical circuit for an AC-coupled analog ADS830 input configuration. All components are powered from a single +5V supply. Connect the RSEL pin to HIGH and the full-scale input range is set to 2Vp-p. In this configuration, the top and bottom references (REFT, REFB) provide output voltages of +3.0V and +2.0V, respectively. Two resistors (2x1kΩ) are used to generate a common mode voltage (VCM) of about +2.5V to bias the input of the driver amplifier. Using the OPA681 on a single +5V supply, the ideal common mode point is +2.5V. This comes at a time when the common-mode input level of the ADS830 is recommended, so there is no need for a coupling capacitor between the amplifier and the converter. Even though the OPA681 has an AC gain of +2, the DC gain is only +1 due to the blocking capacitor on the resistor RG. Adding a small series resistance (RS) between the output of the op amp and the input of the ADS830 will be suitable for almost all interface configurations. This separates the output of the op amp from the capacitive load to avoid gain peaking, which can lead to increased noise. For optimum spurious and distortion performance, resistor values should be kept below 75Ω. The series resistor combined with the 47pF capacitor forms a passive low-pass filter, so limiting the bandwidth of the broadband noise helps improve SNR performance.

AC-COUPLED DUAL SUPPLY INTERFACE The circuit provided in Figure 3 below shows the typical connections for the selected amplifier while operating the analog input with respect to the dual supply. This may be necessary to take advantage of extremely low distortion op amps such as the OPA642. The advantage is that the drive amplifier can swing with a ground referenced bipolar operating signal. This preserves distortion performance. Sufficient headroom for the lowest op amp and supply rails can be maintained as the signal range remains in the linear region. By capacitively coupling a single-ended signal through the input of the ADS830, its common-mode requirement can be easily met by two resistors connected between the top and bottom references.

Simplified circuit timing diagram for input track and hold.

AC-coupled input configuration for 2Vp-p full-scale range and common mode voltage VCM, +2.5V sourced from internal top (REFT) and bottom reference (REFB). The OPA680 can be used in place of the OPA681 if a voltage feedback amplifier is preferred.

AC-couple the dual-supply amplifier OPA642 to the ADS830 for a 2Vp-p full-scale input range.

It is suitable for applications requiring signal amplification provided by a driver amplifier, with a gain of ≥ 5. Consider using an unbalanced voltage feedback operational amplifier, such as OPA643, or current feedback operational amplifiers OPA681 and OPA658. DC-Coupled Level Shifting Several applications may require a bandwidth signal path including DC, in which case the signal must be DC-coupled to the A/D converter. To accomplish this, the interface circuit must provide a DC level shifted analog input signal. The circuit shown in Figure 4 uses a dual-channel operational amplifier A1 to drive the input ADS830 with a level-shifted signal compatible with the selected input range. Connect the RSEL pin to power and the INT/EXT pin to ground, the ADS830 is configured for a 2Vp-p input range and uses an internal reference. Biased using the +2.5V common mode voltage provided at the CM pin. Half of the amplifier (OPA2681) buffers the REFB pin and drives the voltage divider R1, R2. Assuming the noise gain of the op amp is +2V/V.RF = RIN, the common mode voltage (VCM) must be rescaled to +1.25V, resulting in the correct DC level of +2.5V for the signal input (IN). Any DC voltage difference between the IN and IN inputs of the ADS830 effectively creates an offset that can be adjusted to correct for the resistor values of the voltage divider R1 and R2. Criteria for selecting a suitable op amp should include supply voltage, input bias current, output voltage swing, distortion and noise specifications. Note that overall the signal phase is reversed in this example. The original signal polarity is re-established, the IN and IN connections are always interchangeable.

DC-Coupled interface circuit OPA2681 with dual current feedback amplifiers. The OPA2680 can be used in place of the OPA2681 if a voltage feedback amplifier is preferred.

If the application requires signal conversion from a single-ended source to power the ADS830 differentially, an RF transformer can be a good solution. The selected transformer must have a center tap to apply the DC voltage required by the common-mode bias converter input. The AC ground of the center tap will cause the differential signal to swing on the secondary winding. Consider using a step-up transformer to take advantage of signal amplification without introducing another noise source. Additionally, reduced signal swing from the source may result in improved distortion performance.

Differential input configurations can offer significant advantages in achieving good SFDR performance over a wide range of input frequencies. In this mode the impedance of the two inputs to the ADS830 is reduced with closely matched differential signal swings to half the swing required for single-ended driving. The following figure shows the schematic of the proposed transformer-coupled interface circuit. CUIT. The component values of the RC low pass can be optimized according to the desired roll-off frequency. The resistance of the secondary side (RT) should be calculated using the equation RT = n2 x RG to match the source impedance (RG) for good power transfer and VSWR.

The figure below depicts a simplified model of the internal reference circuit. Internal modules are the bandgap voltage reference, the drivers for the top and bottom references, and the resistor reference ladder. The bandgap reference circuit includes logic functions that allow setting the analog input to swing the ADS830 to 1Vp-p or 2Vp-p full-scale by simply connecting the RSEL pin to the LOW or HIGH potential, respectively. When operating the ADS830 in external reference mode, the buffer amplifiers REFT and REFB are disconnected from the reference ladder. As shown, the ADS830 has internal 50kΩ pull-up resistors on the range select pin (RSEL) and reference select pin (INT/EXT). Leaving these pins open configures the ADS830 for 2Vp-p input range and external reference operation. Setting the ADS830 to internal reference mode requires the INT/EXT pin to be driven low. A reference buffer can be used to provide up to 1mA of current (sink and source) to external circuits. To ensure proper operation of any reference configuration, it is necessary to provide robust bypassing at the reference pins to keep clock feedthrough to a minimum (below). All bypass capacitors should be as close to their respective pins as possible.