The CC1050 is a true single-chip UHF transmitter designed for very low power consumption in very low voltage wireless applications. This circuit is primarily intended for use in the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency bands of 315 , 433 , 868 and 915 MHz respectively, but can be easily programmed to operate in other frequency ranges from 300-1000 MHz.

The main operating parameters of the CC1050 can be programmed via an easy-to-interface serial bus, making the CC1050 a very flexible and easy-to-use transmitter possible. In a typical system, the CC1050 will be used with a microcontroller and some external passive components.

application

Ultra Low Power UHF Wireless Data Transmitter

315/433/868 and 915 MHz ISM/SRD band systems

RKE - Remote Keyless Entry

home automation

Wireless Alarm and Security System

AMR - Automatic Meter Reading

low power telemetry

Game Controllers and Premium Toys

feature

True Single Chip UHF RF Transmitter

Very low current consumption

Frequency range 300 - 1000 MHz

Programmable output power -20 to 12 dBm

Small size (TSSOP-24 package)

Low supply voltage (2.1 V to 3.6 V)

Requires very few external components

Single-ended antenna connection

FSK data rates up to 76.8 kBaud

Complies with EN 300 220 and FCCCFR47 part 15

Programmable frequency, 250 Hz steps make crystal temperature drift no TCXO can compensate

Suitable for frequency hopping protocols

Development kit available

Easy-to-use software for generating

CC1050 Configuration Data

A simplified block diagram of the CC1050 is shown in the figure below. Only the signal pins are shown.

The Voltage Controlled Oscillator (VCO) output signal is fed directly into the Power Amplifier (PA). The RF output is the frequency via digital bit stream shift keying (FSK) to pin DI. It is easy to make antenna interface and matching with single-ended PA.

The frequency synthesizer generates a local oscillator signal that is fed to the PA in transmit mode. The frequency synthesizer consists of a crystal oscillator (OSC), a phase detector (PD), a charge pump (CHARGE PUMP), a VCO and frequency dividers (/R and /N). The external crystal must be connected to the XOSC, and only the VCO requires an external inductor. A 3-wire digital serial interface (CONTROL) is used for configuration.

Circuit Description Diagram

Application circuit

Few external components are required for CC1050 operation. A typical application circuit is shown in the figure below. Output matching C1, C2 and L2 are used for matching

The transmitter is 50Ω.

The VCO is fully integrated except for the inductor L1.

Matching component value networks and VCO inductors is easy using SmartRF® Studio metering software.

Crystal oscillators C3 and C4 are load capacitance crystals.

Additional filtering Additional filtering (eg, a low-pass LC filter) may be used to reduce filtered harmonic emissions.

must be used (not shown in application circuit). The placement and size of decoupling capacitors and power supply filtering are very important for optimum performance.

Typical CC1050 Application Circuit

Wire Serial Configuration Interface The CC1050 is configured via a simple 3-wire interface (PDATA, PCLK and PALE). There are 19 8-bit configuration registers, each addressed by a 7-bit address. A read/write bit initiates a read or write operation. A complete configuration of the CC1050 requires sending 19 16-bit data frames each (7 address bits, R/W bits and 8 data bits). The complete required timing configuration depends on the PCLK frequency. A PCLK frequency of 10MHz is fully configured in less than 30µs. Set the device to power

Down mode needs to send only one frame, which in this case will be less than 2 microseconds. All registers are also readable. In each write cycle, 16 bits are sent on the PDATA line. The seven most significant bits of each data frame (A6:0) are the address bits. A6 is the MSB (significant bit for most addresses) and is sent as the first bit. The next bit is the R/W bit (high for writes, low for reads). The transfer PALE (Program Address Latch Enable) in the address and R/W bits must be held low. Then 8 data bits are transferred (D7:0). See below.

The programming time is also shown in the figure above, and the data clock on PDATA is completed on the negative edge of PCLK. When the last bit of the 8 data bits, D0, has been loaded, the data word has been loaded into the internal configuration register. Configuration data is stored in internal RAM and is valid after power-down mode, but not turned off when power is turned on. Registers can be programmed for any order. The configuration registers can also be read from the configuration interface by the microcontroller in the same way. Seven addresses are sent bit first, then data readback is initiated by setting the R/W bit low. The CC1050 then returns the addressed data register. In this case, PDATA is used as an output and must be tri-stated (or set high in the case of an open collector pin by the microcontroller during data readback (D7:0). The read operation is shown below

PCB Layout Recommendations

A double layer PCB is strongly recommended. The bottom layer of the PCB should be the "ground plane". Chipcon provides a reference design that should be followed for best performance. The top layer should be used for signal routing and should be open areas filled with metallization connected to ground using multiple vias. Ground pins should be connected to ground as close as possible to package pins using separate vias. Decoupling capacitors should also be placed as close as possible to the power pins and connected to separate vias to the ground plane. External components should be as small as possible and surface mount devices should be used.

Precautions should be used when placing the microcontroller in order to avoid interfering with RF circuits. In some terrestrial applications where the face of the digital circuit is expected to be noisy, the ground plane may split the analog and digital sections. All AGND pins and AVDD decoupling capacitors should be connected to the analog ground plane. All DGND pins and DVDD should be decoupling capacitors connected to digital ground. The connection between the two ground planes should be a star with a power ground connection. A fully assembled development kit PCB is available that can be used as a layout guide.

Antenna Considerations

The CC1050 can be used with various antenna types. The most common antennas used for short-range communications are monopole, helical and loop antennas. A monopole antenna is resonant with a length corresponding to one quarter of the electrical wavelength (λ/4) of the antenna. They are easy to design and

Can simply be implemented as a "piece of wire" or even integrated into a PCB. A shorter non-resonant monopole can also be used with λ/4, but the cost ranges. Size and cost are critical applications such an antenna may be very well integrated into a PCB. A helical antenna can be thought of as a combined monopole and loop antenna. They are a good compromise for scale-critical applications. But helical antennas are often harder to outperform simple monopoles. Loop antennas are easy to integrate with PCBs, but have poor impedance matching due to their very low radiation resistance. For low power applications, λ/4- is recommended to give the best range for a monopole due to its simplicity.

The length of a λ/4 monopole antenna is given by: L = 7125 /f where f is in MHz and the length is given in cm. The 869 MHz antenna should be 8.2cm, 16.4 cm, 434 MHz.

The antenna should be connected as close as possible to the IC. If the antenna is located far from the input pins the antenna should match the feed to the transmission line (50Ω).