Features On-Chip Predictive Gate Drive Operation of High Efficiency Synchronous Bucks Dual 3-A TruedDrive Outputs ±1 MHz High Frequency Operation, 70 ns Delay from Synchronous to G1 Output Leading Edge Modulation -3 Mode Operation with V to 35-V Deviation Output Stage Reverse Current Protection User Programmable Shutdown ±1.0% Initial Tolerance Band Gap Reference High Bandwidth Error Amplifier Thermally Enhanced HTSSOP 20-pin PowerPad Package Simplifies Application Diagram Application Multiple Output Secondary Side Column Regulation (SSPR) Cascaded Buck Converters for Power Supplies Bus Post-Processing Converters Converter and DC Transformer Architecture Description
The UCC2540 is a secondary-side synchronous step-down PWM controller for high current and low output voltage applications. It can be used either as a local secondary-side controller for isolated DC-DC converters using a two-stage cascade topology, or as a secondary-side post-regulator (SSPR) for multiple output supplies.
The UCC2540 operates with a synchronous signal from the primary side or the high duty cycle quasi-DC output of a bus converter or DC transformer. To improve efficiency, it also incorporates predictive gate drive techniques that virtually eliminate body diode conduction losses in synchronous rectifiers.

Description (continued)
The UCC2540 is available over an extended temperature range of -40°C to 105 °C and is available in a thermally enhanced PowerPad 20-pin HTSSOP (PWP) package. This space-saving package in a standard 20-pin TSSOP package features a significantly reduced thermal resistance of 1.4°C/Wθ to accommodate dual high-current drivers on board. JC
Absolute Maximum Ratings Operating Free Air Temperature Range Excessive (unless otherwise noted)

NOTE: The PowerPad does not have any leads directly connected to the pack. It is electrically and thermally connected to the device's substrate as ground and should be connected to pgnd on the printed circuit board. Exposed dimensions are 1.3 mm x 1.7 mm. However, due to variations in position and die flow, the tolerance can be +1.05 mm/-0.05 mm (+41 mils/-2 mils).

Functional block diagram

1) REF is an input in mode 3 only.

The UCC2540 is a high-efficiency synchronous buck controller that can be used in many point-of-load applications. It can act as a local controller for cascading technologies such as post-processing converters for isolated integrated bus converters (IBCs) and DC transformer architectures. It can also be used as a general-purpose secondary side post regulator for high-precision multi-output power supplies.

Using UCC2540 as a Secondary Side PWM Controller for Cascaded Push-Pull Buck Secondary Converters

The two-stage cascaded push-pull buck topology converts higher input bus voltages, such as 48-V telecom voltages, to output voltages below 2-V.

figure 2. Secondary Side Controlled Cascade Push-Pull/Buck Converter

The primary-side power stage is an open-loop push-pull converter that provides voltage step-down and galvanic isolation. This will take the high bus voltage and convert it to an intermediate voltage like 7 V. The primary side push-pull gate drive signal can come from an off-the-shelf oscillator or a fully integrated 50% load dual output oscillator such as the UCC28089.

The secondary side power stage is a buck converter optimized for low output voltage regulation. The clock reset pulse signal on the primary side is transmitted through the signal transformer.
This secondary side control circuit has many advantages. Simple isolated power stages do not require any feedback across the isolation boundary. Since the primary side oscillator is free-running, an isolated startup power supply is not required. This high frequency circuit provides soft switching operation (all six MOSFET switches), optimal transformer core utilization, and minimizes filter requirements because there are no additional high current inductors.

The push-pull primary side allows simple direct drive control of the input stage MOSFETs. In exchange, it requires the input MOSFET to be rated at least twice the peak input line voltage. This configuration is suitable for 36-V to 72-V input line applications because many suitable power MOSFETs are available in the 150 V range. For applications with larger input voltages, a half or full bridge with AC modulation may be more suitable for the input stage. Therefore, the cascade topology has great flexibility for the input power stage. The cascade topology also has flexibility in the output stage.

For more information on this topology, see Power Symposium SEM-1300 Topic 1: Unique Cascaded Power Converter Topologies for High Current Low Output Voltage Applications [1]. This topic discusses how it works, design tradeoffs, and key design procedure steps.

UCC2540 in a multi-output power supply

One such flexibility is the ability to easily add independently adjustable auxiliary outputs. A multi-output implementation of a cascaded push-pull/buck power converter is shown in Figure 3.

image 3. Multi-Output Implementation of Push-Pull/Push-Pull Cascaded Converters

Using the UCC2540 as a secondary jamb adjuster

The UCC2540 can also be used as a secondary side post regulator (SSPR) to precisely regulate the auxiliary voltage of multiple output supplies, as shown in Figure 4. The UCC2540 uses leading-edge modulation, so it is compatible with voltage-mode or current-mode primary-side controlled converters, using any topology such as forward, half-bridge or push-pull.

Figure 4. Multi-Output Converter with Primary Push-Pull Converter

CEA and VEA pins: current limit and hiccup mode

Typical power supply load voltage and load current are shown in Figure 5. This figure shows steady-state operation from no load to overcurrent shutdown (soft-start retry is not depicted in the figure). Under voltage regulation conditions, the output of the voltage error amplifier is lower than the current error amplifier, allowing the voltage error amplifier to control operation. Under current limit conditions, the current error amplifier output is lower than the voltage error amplifier, allowing the current error amplifier to control operation. The boundary between voltage and current control occurs when the difference between CEA and VEA attempts to exceed 50 mV.

Current limiting begins to occur when the difference between CEA- and VEA- exceeds 50 mV. For currents above this operating condition, the UCC2540 controls the converter to operate as a pure current source until the output voltage drops to half its rated steady-state level. The UCC2540 then sets the G1 and G2 outputs low and latches on to a fault that discharges the soft-start voltage at a 30% charge rate. The UCC2540 prohibits retries until the soft-start voltage drops below 0.5 V. A functional diagram of the voltage and current error amplifiers is shown in Figure 6.

COMP, VEA−, and CEA− Pins: Voltage and Current Error Amplifiers

From no load to full rated load operating conditions, the UCC2540 operates as a voltage mode controller. Above the programmed rated current, there are two levels of overcurrent protection: constant current limit and overcurrent reset/retry. This section gives advice on how to design voltage and current controllers so that they interact in a stable manner. See the functional diagram of the voltage and current error amplifiers in Figure 6. The voltage error amplifier in the figure shows three non-inverting inputs. Add the lowest of the three non-inverting inputs (1.5 V, SS, and TR) to the non-inverting input to obtain the voltage error signal. The lowest of the two outputs drives the inverting stage, which in turn drives the modulator.

During steady state voltage control, the feedback element in the current loop has no effect on the loop stability. When the current limit occurs, the voltage error amplifier is effectively turned off and the current error amplifier takes control. In steady state current limiting operation, the negative feedback element in the voltage error amplifier loop becomes the positive feedback element in the current error amplifier loop. For the current error amplifier to be stable, the impedance in the feedback path of the current error amplifier must be lower than the impedance in the feedback path of the voltage error amplifier. This means that the resistance in the negative feedback path of the current error amplifier must be smaller than the resistance in the negative feedback path of the voltage error amplifier. Also, the capacitance in the negative feedback path of the current error amplifier must be larger than the capacitance in the negative feedback path of the voltage error amplifier. (Capacitance is actually an admittance value, not an impedance value). This concept is shown in Figure 6.

For stability in the current loop, _Z_ must be less than _Z_ at all frequencies. if r c, then this can be achieved. IVFVFIFVFIFV
Another problem that can occur during current limit operation is the stability of the modulator. For the modulator to stabilize, the rising slope of the current ripple measured at the comp pin must be less than the rising slope measured at the ramp pin. This can be achieved by choosing the ratio of z to z, or by a capacitor in parallel with R and C (like C) in Figure 6. ⅣFVFIFI Fir Tree Stable Dynamic Current Loop Design

1. Using any common method, design a voltage error amplifier for a regulated voltage mode design. Use at least 15 kΩ for any resistors in the voltage error amplifier negative feedback path (between pins 9 and 7). This does not apply to the resistance value between the power supply output voltage and pin 7; nor does it apply to the resistance value between ground and pin 7.

2. Its purpose is to design the current limit control loop to drive the converter to maintain 50 mV between the VEA pin and the CEA pin under current limit conditions. The VEA-to-ground and CEA-to-ground current sense element and divider ratios are chosen to provide the desired level of current limit.

3. Place the same part configuration in the negative feedback path of the current error amplifier (between pins 9 and 8) as in the negative feedback path of the voltage error amplifier (between pins 9 and 7). However, the resistor value used is 67% of the corresponding resistance between pins 9 and 7, and the capacitor value used is 150% of the corresponding capacitance between pins 9 and 7.

4. Check the compressor signal. If unstable, place a capacitor (or add more) between pins 9 and 8 to reduce current ripple. Increase the value of the capacitor until the compensation pin voltage stabilizes. Compare the offset voltage and the ramp voltage. In the case of stable operation, the rising slope of the compensation voltage ripple is smaller than the rising slope of the ramp pin.
RSET, RAMP, G2C, SS pins: programming timer current

Set the timer's base current with a resistor from RSET to GND. The block diagram of the UCC2540 shows the interaction of the RSET pin with the associated current sources for ramp, G2C and SS characteristics. The RSET pin is a voltage source; the current at the RSET pin is reflected and multiplied by the gain and then distributed to the ramp (gain=2), G2c (gain=2) and ss (charge gain=1.33, net discharge gain=0.4). Resistors applied across the RSET pin and GND should be 10 kΩ

g2c pin: g2 timer
UDG 04047
G2 timer function diagram
The G2C pin programs the maximum duration of the synchronous rectifier for low duty cycle or zero duty cycle operation. Figure 8 shows the functional diagram. This function is programmed by connecting a capacitor between the G2C pin and GND. The capacitor on G2C should be slightly larger than the capacitor on the ramp pins. For best results, program a typical G2 time limit between 1.5 and 3 times the switching period (T). Note that both g1 and g2 are forced to low outputs when the g2 timer reaches its limit. This feature prevents the current in the output inductor from being too negatively offset under zero duty cycle conditions. The g2 timeout (g2to) duration is programmed using equation (1): 2 VRSETG2 timeout duration V = 1.5 V (TYP) RSET1.5 t The ramp pin serves two purposes: (1) to program the gain of the PWM regulator; (2) to program the timeout period G1 when the main power stage does not result in a sync pulse. Figure 9 shows a schematic diagram of the PWM modulator and G1 timer.

The UCC2540 has a leading edge modulator that compares the error output to the ramp voltage. The modulator frequency is driven externally through a sync pin. The ramp pin provides a sawtooth wave for the PWM comparator, which acts as a G1 timeout protection programmed by R and the value of the ramp capacitor. The aggregate switching cycle begins with the falling edge of the sync signal, which must be at least 50 nanoseconds lower. The falling edge of Syncin generates a 100 ns discharge strobe (CLK) to the ramp function, which then allows the ramp capacitor to charge from the 2 × I current source. RSET

In order to use the G1 timer function, the peak ramp voltage at the end of the switching cycle should be close to the 2.5 V allowed by the c tolerance. In other words, the PWM modulator gain should be programmed to be equal to or slightly greater than 0.4 inverse V. Ramp and RRSET sync pins

The falling edge applied to the sync pin generates a narrow pulse that is the basic timer for the internal UCC2540 functionality. A sync pulse must be high at least 100 ns before the falling edge and low at least 50 ns before the falling edge to register as a valid pulse. Due to the critical nature of timing, avoid filtering the falling edge of the sync signal to avoid signal delays. The peak sync voltage can easily vary from 2.5 V to 6.6 V, which allows a simple resistor divider to scale the secondary transformer voltage in post-regulator applications.

Clamping and/or additional gain may be required in the case of larger line voltage variations or where there is a lot of ringing.

ground clamp

In applications where loops or spikes cause SYNCIN to be lower than GND, protect the pins with Schottky diodes (cathode = SYNCIN, anode = GND).

overvoltage clamp

In applications where the peak sync voltage is dangerously close to the absolute maximum level of 8 V due to ringing or voltage levels, overvoltage clamping of the sync signal may be required. REF or VDRV can be used as a clamping voltage, ensuring that REF or VDRV is always a current source. The reason for this is that both REF and VDRV are used to detect the mode of operation when back-driven, and they may lock into the wrong mode of operation at startup.

Another overvoltage clamping option is to clamp the sync pins directly. Unfortunately, the junction capacitance of the Zener diode is too large, causing too much signal delay. However, base-emitter clamping can be used with minimal synchronization signal delay to achieve the desired clamping action. Simply select R and (R+R) to provide an appropriate 0 V to 3.3 V signal for low-side line conditions. Then, the ratio of r to r is chosen so that the transistor turns on when the sync voltage exceeds 4V. Strontium carbon black is carbon black is

Synchronous Clamping for Isolated Cascaded Buck Topologies

When the UCC2540 cooperates with the UCC28089 primary side start-up controller, it is very suitable as a secondary side controller for a cascaded Buck topology. The master side controller sends pulse edges within its dead time. The UCC2540 uses primary side pulses to provide zero-voltage conditions for the primary and secondary side switches. The predicted delay characteristic adjusts the secondary-side transition to minimize reverse recovery losses of the synchronous rectifier. The pulse edge information may vary with the primary bias voltage, so it must be clamped. The circuit shown in Figure 12 includes appropriate pulse edge shaping circuitry, clamping, and 1500-V isolation. The recommended transformer coev part mgbbt−00011−01 is smaller than many opto-isolators.

VDD, VDRV, VREF, and BST Pins: Operating Modes

Start-up, shutdown, and restart conditions vary depending on the available bias for the UCC2540. The UCC2540 has three different biasing configurations or modes. This mode is detected during power-up and latched into an internal register when VREF exceeds 2 V. This register is cleared when VDD, VDRV and VREF are simultaneously less than 1 V. All modes are compatible with cascaded buck or secondary side post regulator (SSPR) topologies. The main bias voltage for Mode 1 and Mode 2 can be achieved by diodes and capacitors for AC voltages such as the secondary winding of a transformer. Table 1 lists a summary of the modes and their programming requirements.

Mode 1 or normal operation requires the available bias voltage of the device to be 8.5 V or higher. Here, the bias voltage drives the VDD pin. The low-side drive bias, V=7V, is generated by an internal linear regulator, which draws current directly from the VDD pin. The high-side driver bias is a flying capacitor that charges from the VDRV pin through the G2 pin through the diode between G2 and BST when G2 is Hi. When V is higher than 2 V, the UCC2540 operates in Mode 1 if V > (V and V). Mode 1 allows a maximum range of bias voltages, from 8.5 V

Mode 2 is suitable for applications where the bias voltage is typically 5 V (4.5 V to 8.0 V). Bias is applied to the VDRV terminal of the UCC2540. The high side driver bias is a flying capacitor that charges from the vdrv pin through the g2 pin when g2 is hi. Biasing to the VDD pin is obtained through an external voltage doubler charge pump. If the system uses low threshold voltage power MOSFETs, VDD can be connected directly to the VDRV pin. The bias voltage can be the bus converter output or auxiliary power supply, or the reflective converter input voltage, which is derived from the regulation source.

Mode 3 is suitable for synchronous buck converter applications where the bias is a regulated 3.3-V supply. This is the main output voltage commonly found in multiple output power converters. Bias is applied on the VREF pin of the UCC2540. If the UCC2540 detects (V and VDD) when V is higher than 2 V, it operates in mode 3. VREF > V voltler virus VREF
Combinations of various modes and biasing schemes. In Mode 1 and Mode 2, the bias voltage can be an independent auxiliary power supply, or it can be generated by correcting and filtering the reflected line voltage, as shown in Figure 13 to Figure 16. Regulated auxiliary power must be used with Mode 3 because the tolerance of the VREF voltage is the control tolerance of the UCC2540. In Mode 3, the regulated auxiliary power can be independent of the power input voltage or the regulated auxiliary power can be the same as the power input voltage.

Charge Pump Capacitor Selection

Capacitors C1 to C5 are all part of the charge distribution network that allows the UCC2540 to pass charge to the MOSFET gates of Q1 and Q2. This section gives guidelines for choosing the values of C1 to C5 for proper operation of the converter. Due to MOSFET characteristics, diode d1-d4 characteristics, and closed-loop converter performance, specific capacitor values may need to be larger than recommended. All three operating modes require a charge-pump capacitor and diodes C1 and D1 to drive the high-side power MOSFET. Modes 2 and 3 require additional charge pump capacitors and diodes to supply voltage to VDD. In general, all charge pump diodes should be Schottky diodes in order to have low forward voltage and high speed. Charge pump capacitors should be ceramic capacitors with low effective series resistance (ESR), such as X5R or X7R capacitors.

The value of the charge pump capacitor c1 depends on the charge and capacitance of the power FET gate, the voltage level of the Miller plateau threshold, the forward drop of d1 and the closed loop response time. The unloaded high-side gate driver typically draws 2 nc of charge per rising edge, plus 30 µA DC from C1. Typically, the unloaded high-side gate driver load is small compared to the gate charging requirement q1 of the high-side power MOSFET. A typical value of C1 is about 50 to 100 times the input capacitance (C) of MOSFET Q1. This typically allows for transient operation at very large duty cycles where C1 does not have enough time to fully charge. If C1 is too large, its ESR and ESL prevent it from charging during transients, including startup transients. International Space Station

Capacitors C2 to C5 are then selected based on the direction of charge transfer and the requirements of the UCC2540. Keep in mind that the design of each converter may require adjustments compared to the larger capacitor ratios recommended. The selection process starts from the left side of Table 2 and proceeds to the right side of the table, which is the reverse order of the charge flow initiating the first few cycles. If iterations are required during the design process, review the progress of the capacitors in the order shown in the table from left to right.

The VDD filter capacitor C4 must supply the Iidle current to the UCC2540 (about 11 mA), plus the charge driving the gates G1 and G2. Capacitor C4 must be large enough to maintain sufficient operating voltage at full operating IVDD current during startup and other transients. Knowing the operating frequency and the MOSFET gate charge (Q), the average I current can be estimated as: VDDGVD where f is the switching frequency S To prevent noise problems, C4 must be at least 1 microF. Also, it has to be large enough to pass the charge to the power MOSFET gate. So C4 typically requires a capacitive output stage with at least twice the vdrv filter capacitors

The UCC2540 includes dual gate drive outputs, each capable of ±3-A peak current. The pull-up/pull-down circuits of the driver are bipolar transistors and MOSFET transistors in parallel. The high-side and low-side dual drivers provide a true 3-A high-current capability in the MOSFET's Miller plateau switching region, where it is most needed. The peak output current rating is the combined current from the bipolar transistor and the MOSFET transistor. When the voltage on the drive output is less than the saturation voltage of the bipolar transistor, the output resistance is the R of the MOSFET transistor. DS

The output driver can be switched from VDD to GND. Each output stage also provides a very low impedance overshoot and undershoot. This means that in many cases, external Schottky clamp diodes are not required. The output is also designed to withstand 500mA of reverse current without damaging the device or malfunctioning logic.

Predictive Gate Drive TechnologyTM
Gate drive techniques are predicted to maximize efficiency by minimizing body diode conduction. It utilizes a digital feedback system to detect body diode turn-on and adjusts the dead-time delay to minimize the turn-on interval. This closed-loop system virtually eliminates body diode conduction while adjusting for different FET, temperature and load dependent delays. Since power dissipation is minimized, higher switching frequencies can be used, resulting in smaller component sizes. Precise gate timing on the nanosecond scale reduces the reverse recovery time of the body diode of the synchronous rectifier MOSFET, thereby reducing the reverse recovery losses seen in the main (high side) MOSFET. Finally, lower power consumption increases reliability.

The soft-start interval begins when the UCC2540 recognizes that an appropriate voltage (see Mode 1, 2, or 3) is above the UVLO level. Then, the voltage of C increases linearly until it is clamped to the reference voltage of 3.3V. Regulation should be reached when the soft-start voltage reaches about 2.2V (1.5V plus diode drop). Use Equation (5) to select a C capacitor value to program the desired soft-start duration. If a UVLO fault is encountered, both outputs of the UCC2540 will be disabled and the soft-start pin (SS) will discharge to GND. The UCC2540 will not retry until the uvlo fault is cleared.
Using the TR pin, the UCC2540 can be programmed to track another converter output voltage. If the voltage to be tracked is between 0 V and 3.3 V, simply connect the TR pin to the voltage to be tracked using a resistor approximately equal to the DC impedance connected to the VEA- terminal). If the voltage is above this range, again use a voltage divider with an equivalent resistance approximately equal to the DC impedance connected to the VEA- terminal. Other strategies can be used to implement sequential, ratiometric or synchronous power tracking].
The implementation of sequential ordering of multiple output power supplies is shown in Figure 21. Applications with loads including processors with a core voltage of 1.5 V and I/O ports requiring 3.3 V may require sequential ordering to resolve system-level bus contention during startup. In this case, the core must be powered up first, and then after an initialization period of 130 ms, the port can be powered up.

Using the TR pin, the UCC2540 can be programmed to track another converter output voltage at a measured ratio. Ratiometric tracking is when the ratio of the output voltage is constant from zero volts to one or more points where the output locks in regulation. Compared to SS pins, TR pins are easier to use for tracking because external currents applied to SS pins may interfere with SS discharge current and fault recovery. It should be understood that the voltage being tracked must lag the bias voltage (vdd, vdrv and ref) at startup and lead the bias voltage during shutdown. In addition, the tracked output must not reach its steady-state DC level before the tracked output reaches its steady-state DC level. The general circuit for programming the UCC2540 to track the lead supply voltage with a tracking ratio A is shown in Figure 24. To program trace profile gains g and g, follow the ratiometric trace design process listed below. The special case of simultaneous sequencing with V>1.5V is the simplest design; no need to set R=R and R=R,G. In many other cases, the circuit can be simplified by removing the op amp with G and Zener clamping diodes. If an op amp is required, it should be capable of rail-to-rail operation, usually with low voltage bias; for both requirements, the TLV271 is an inexpensive solution to the tracking circuit and also has a soft-start capacitor C. A soft-start capacitor can be used to limit the time between short circuit retry attempts, and it prevents overshoot when recovering from a fault where only the tracking supply, not the mains supply.

Related Products

UCC28089 Primary Side Push-Pull Oscillator
UCC27223 High Efficiency Predictive Synchronous Buck Driver
UCC3583 Switch Mode Secondary Jamb Regulator
UCC25701 Advanced Voltage Mode Pulse Width Modulator
UCC3808A Low Power Current Mode Push-Pull PWM
UCC38083/4/5/6 8-pin current mode push-pull PWM with programmable slope compensation

1. Power Symposium SEM-1300 Topic 1: Unique Cascaded Power Converter Topologies for High Current Low Output Voltage Applications, by L. Balogh, C. Bridge and B. Andreycak (SLUP118)

2. Power Symposium SEM-1400 Topic 2: L.Balogh's (SLUP133) High-Speed MOSFET Gate Drive Circuit Design and Application Guide

3. Datasheet, UCC27223 High Efficiency Predictive Synchronous Buck Driver (SLUS558)

4. Datasheet, UCC37323/4/5 Dual 4-A Peak High Speed Low-Side Power MOSFET Drivers (SLUS492A)

5. Power Symposium SEM1600 Topic 2: Power Sequencing in Multiple Voltage Rail Environments, D.Daniels, D.Gehrke and M.Segal (SLUP224)

6. Technical Brief, PowerPad Thermal Enhancement Package (SLMA002)

7. Application Introduction, PowerPad Simplified, (SLMA004)

8. Datasheet, TPS3103K33 Ultra-Low Supply Current/Supply Voltage Supervisory Circuit (SLVS363)

9. Application Note, A Revolutionary Power Management Solution for High Efficiency, Multiple Output Applications, by Bill Andreycak, (SLUA255)

10. Application Note, Predictive Gate Drive FAQ by Steve Mappus (SLUA285)