The AD9200 is a single-chip, single-supply, 10-bit, 20 MSPS analog-to-digital converter amplifier and voltage reference with on-chip sample-and-hold. The AD9200 uses a multi-stage differential pipeline architecture, 20 MSPS data rate and guaranteed no missing code range over the entire operating temperature.

The inputs to the AD9200 are designed to simplify the development of imaging and communication systems. The user can select various input ranges and offsets, and can drive the inputs as single-ended or differential. Sample-and-hold (SHA) amplifiers are equally suitable for both multiplexing systems, switching full-scale voltage levels in continuous channels and at frequencies up to and beyond the Nyquist rate for single-channel inputs to sample. The AC-coupled input signal can be converted to a predetermined horizontal clamp circuit (AD9200ARS, AD9200KST) by on-board. Dynamic performance is excellent.

The AD9200 has an onboard programmable voltage reference. An external reference can also be selected to accommodate applications with DC accuracy and temperature drift requirements. A single clock input controls all internal conversion cycles. Digital output data presents the output format in straight binary form. The out-of-range signal (OTR) represents an overflow condition that can be used with the most significant bit to determine low or high overflow.

application

The AD9200 operates from 2.7 V to 5.5 V, making it ideal for high-speed, low-power operation in portable applications.

AD9200 industrial specification (-40°C to +85°C) and commercial (0°C to +70°C) temperature range.

Product Highlights

low power

The AD9200 consumes 80 mW from a 3 V supply (excluding reference power). In sleep mode, the power is reduced to below

5 mW. very small packaging

The AD9200 is available in 28-pin SSOP and 48-pin LQFP packages. Pin compatible with AD876

The AD9200 is pin compatible with the AD876, allowing older designs to move to lower supply voltages. The 300 MHz onboard track-and-hold multifunction SHA input can be configured as single-ended or differential input.

Out of Range Indicator The OTR output bit indicates when the input signal is outside the input range of the AD9200.

Built-in clamp function allows direct recovery of video signal AD9200KST using AD9200ARS and DC92

Functional block diagram

AD9200 Specifications (AVDD = +3 V, DRVDD = +3 V, FS = 20 MHz (50% duty cycle), MODE = AVDD, 2 V Input Range 0.5 V to 2.5 V, external reference unless otherwise noted Voltage, TMIN to TMAX.

Parameter Sign Min Typical Max Unit Conditions

Resolution 10

Conversion rate FS 20 MHz

DC accuracy

Differential nonlinearity DNL±0.5±1 LSB REFTS = 2.5 V, REFBS = 0.5 V.

Integral nonlinearity INL±0.75±2 LSB

Offset Error EZS 0.4 1.2%FSR

Gain Error EFS 1.4 3.5% FSR

reference voltage

Maximum reference voltage REFTS 1 AVDD V.

Bottom reference voltage REFBS GND AVDD - 1 V.

Differential reference voltage 2 V pp

Reference input resistance 110kΩ REFTS, REFBS: MODE = AVDD

4.2kΩ between REFTF and REFBF: MODE = AVSS

analog input

Input Voltage Range AIN REFBS REFTS V REFBS Min = GND: REFTS Max = AVDD

Input Capacitance CIN 1 pF Switching

Aperture delay tAP 4 ns

Aperture uncertainty (jitter) tAJ 2 ps

Input bandwidth (-3 dB) BW

Full power (0 dB) 300 MHz

DC leakage current 23μA input = ±FS

internal reference

Output voltage (1 V mode) VREF 1 V REFSENSE = VREF

Output voltage tolerance (1 V mode) ±10±25 mV

Output Voltage (2 V Mode) VREF 2 V REFSENSE = GND

Load regulation (1 V mode) 0.5 2 mV 1 mA load current

power supply

Operating voltage AVDD 2.7 3 5.5 V.

DRVDD 2.7 3 5.5 V

Supply current IAVDD 26.6 33.3 mA AVDD = 3 V, MODE = AVSS

Power dissipation PD 80 100 mW AVDD = DRVDD = 3 V, MODE = AVSS

Power down 4 mW STBY = AVDD, MODE and CLOCK =

AVSS

Gain Error Power Supply Rejection PSRR 1% FS

Dynamic Performance (AIN = 0.5 dBFS)

Signal-to-noise ratio and distortion SINAD

f = 3.58 MHz 54.5 57 dB

f = 10 MHz 54 dB

valid bits

f = 3.58 MHz 9.1 bits

f = 10 MHz 8.6 bits

SNR

f = 3.58 MHz 55 57 dB

f = 10 MHz 56 dB

Total Harmonic Distortion THD

f = 3.58 MHz -59 -66 dB

f = 10 MHz -58 dB

Spurious Free Dynamic Range SFDR

f = 3.58 MHz -61 -69 dB

f = 10 MHz -61 dB

two-tone intermodulation

Distortion IMD 68 dB f = 44.49 MHz and 45.52 MHz

Differential Phase DP 0.1 Degree NTSC 40 IRE Mod Ramp

Differential Gain DG 0.05%

PIN configuration

28-Lead Shrink Small Outline (SSOP) Diagram

48-Pin Plastic Low Profile Quad Flat Package (LQFP) Diagram

Definition of Specifications

Integral Nonlinearity (INL)

Integral nonlinearity is the line code where each individual's deviation goes from "zero" to "full scale". The point used as "zero" occurs 1/2 LSB before the first transcoding. "Full scale" is defined as 1 1/2 LSB code transitions beyond the last stage. The deviation is each specific code measured from the center to a true straight line.

Differential Nonlinearity (DNL, No Missing Codes) Ideal ADCs have code transitions separated by exactly 1 LSB. DNL is the deviation from this ideal value. Often this is guaranteed under the No Missing Code Resolution (NMC).

offset error

The first transition should occur at 1 LSB level above "zero".

The offset is defined as the deviation of the actual first code transition from that point. Gain Error For an analog value of 1 LSB, the first code transition should be made above the nominal negative full scale. The final transition should occur where the analog value is below the nominal positive full 1 LSB scale. Gain error is the deviation of the actual difference between the first and last transcoding from the ideal difference between the first and last transcoding. Pipeline Latency (Latency) Number of clock cycles between conversion start and conversion

The relevant output data is available. The new output provides data on every rising edge.

Theory of Operation

The AD9200 uses a pipelined multistage architecture to achieve high sampling rates at low power. As the AD9200 refines the conversion by distributing the conversion over several smaller A/D sub-blocks, the accuracy gradually increases from stage to stage. As a result of the distributed conversion, the AD9200 requires only a fraction of the 1023 comparators used in conventional flash-type A/Ds. A sample-and-hold function within each stage allows the first stage to operate on new input samples, while the second stage, the third stage, and the fourth stage operates on the first three samples.

mode of operation

The AD9200 is designed for optimum performance in a wide variety of imaging, communications and instrumentation applications, including pin compatibility with the AD876 A/D. To achieve this flexibility, the AD9200's internal switches are used to reconfigure the circuit into different modes. These modes are selected with appropriate needle ties. There are three parts of the circuit affected by this modality: the voltage reference, the voltage reference buffer, and the analog input. The nature of the application will determine which mode is appropriate: the descriptions in the following sections and Table I should thus assist in selecting the desired mode.