Source Loop Controller Characterization
Provides control for flyback based the UCC3750 source ringer controller provides a complete control and four-quadrant amplifier topology driving solution for a four-quadrant feedback loop generator circuit. Tea Onboard sine wave reference with low cost is where it goes from input to output. IT also controls the switching power flow of the primary side switch forward synchronous rectification switch when modulating the two secondary power transfer with a selectable cycle frequency. When the power is pulse width modulated, the switches are pulse width modulated. Different phone systems UCC3750 has an onboard sine wave reference with programme 20Hz, 25Hz and 50Hz programmable output amplitude and frequency DC offset high frequency (32khz) crystal connected externally. Short circuit for two frequency DC current limiters Quency-Select Pins Controller internally split to provide sinusoidal output protection 20 Hz, 25 Hz or 50 Hz. The loop generator can also be used for other frequencies by providing an external generator to the chip Sine wave or lock the crystal input at a fixed frequency at multiple fixed frequencies via a second side voltage mode. Controlling other features includes a programmable DC current amplifier in the UCC3750 adding a programmable DC offset to the output voltage. Tea also provides an uncontrolled amplifier (AMP) for other signals.
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Absolute Maximum Ratings Connection Diagram Maximum Forced Voltage Input Supply Voltage Maximum Forced Voltage………–0.3V to 7.5V GD1 2 27 Enbl
Maximum forced current…………Internal limit GND 3 26 GD3
Maximum Forced Voltage………–0.3V to 7.5V VCP 4 25 Reference Voltage Maximum Forced Voltage………–0.3V to 7.5V Maximum Forced Voltage………–0.3V to 7.5V VDD 7 22 XTAL1
Output current (gd1, gd2, gd3) swrly 8 21 xtal2
Pulse…………1.5as INR 9 20 fs0
Storage temperature…………–65°C to + 150 °C
Junction Temperature………–55°C to +150°CS Into 10 19 fs1
Lead temperature (soldering, 10 seconds) +300°C outdoor 11 18 neg2

Unless otherwise stated, voltage refers to ground negative DC negative 1 12 17, current is positive input, and negative output specifies the terminal. Pulses are defined as less than 10% duty cycle and the amplifier output is 13 16 outputs 1.

DescriptionPIN
Ampin: Inverts the input of an uncommitted amplifier. Table 1 Frequency Selection Table Ampout: The output of the uncommitted amplifier. (for 32kHz crystal). CT: This pin programs the internal PWM oscillator FS0 FS1 SINREF (Hz) frequency. The capacitor from CT to GND sets the charge to 0 0 20 and the discharge time of the oscillator ENBL: Logic input, makes the output and 11 high impedance when the pump is charged at high voltage. ENBL should be pulled low to turn off the output. GD1: The output driver that controls the primary side switch The frequency selection pin of the flyback converter through the gate drive transformer.
Sine wave generator. The output signal on this pin is a positive PWM. Frequency as a function of fs0 and fs1 is zero in 32kHz power delivery mode and zero at negative power. crystal for crystal input (xtal1, xtal2). Other proportional frequencies of transmission modes can be passed through different crystals. Inputs fs0 and fs1 are TTL compatible.

Pin Description (continued)
Output driver for the internal 7.5 V reference. For best results, bypass the side switch in the flyback converter. Use ceramic capacitors (>0.1µF) to output signals on GND. A positive reference signal and input are output during Mode 1. This pin acts as a synchronous rectifier. The reference signal is negative and is returning to the power amplifier output in range (0 Positive power delivery. Logically, this output is the opposite of RT: a resistor from RT to GND helps set the oscillator. Provides the correct polarity drive signal for the P channel frequency. RT programming charge and discharge switch. CT current. Output driver that controls n-channel secondary sinflt: This signal is a buffered version of sinref. Side switch in a flyback converter. The output signal on this signal is summed with the DC offset level in Mode 2, when the scale is appropriate, this pin is PWM.
Power is returned to sinref: this pin is the output of the sine wave to the input. This pin functions as a synchronous rectifier reference generator. During Mode 3, it has a high output impedance output, a 0.01µF capacitor is recommended to ground, and positive power transfer. Provides smoothing of sine waves. When fs0 and fs1GND: the reference points for the internal reference, all are set high and the sine reference generator is the threshold. A signal return path is also provided for all disables, allowing this pin to accept an external sine wave on the other pins. enter. Negative 1: Inverting input of the buffer amplifier, acting as a swrly: logic output that causes battery offset to allow the summing junction of the DC (battery) offset voltage crossing point (typically 5ms) of the "zero volt" relay. and sine wave reference. switch. This pin typically draws 250µA. Negative 2: Inverting input of error amplifier, where XTAL1: Crystal connection for external crystal. The output voltage and reference signal from this pin ringer can also be used to clock the internal sine wave. Apply the desired offset using a weighted sum. Generator when XTAL2 is connected to VDD/2. The feedback compensation is connected between the neg2 xtal2:crystal connections of the external crystal. and output 2. VCP: Externally connected current limit for charge pump storage.
Negative DC: The inverting input of the amplifier for the DC capacitor. Recommended capacitor ≥ 2.2 mf to reduce the output ripple of the oil charge pump. The voltage at this pin is output 1: the output of the buffer amplifier, which provides the scaling used by the output driver for the gate drive voltage. As well as filtering the reference signal before feeding it to the alternating gate drive voltage (>10V). error amplifier. This output is also used to make an internal connection at this pin when leaving the priming pump. Select the PWM mode of the flyback converter. The circuits of nodes vs1, vs2 are disconnected. Output 2: The output of the error amplifier. Used to connect to VDD: External power input used to bias internal logic components. The absolute value function of this output. A regulated 5V supply is usually connected to determine the duty cycle of the PWM pulses. Polarity between this pin and ground. It is also the input voltage which also determines the PWM mode. The output of the voltage tripling circuit that produces the gate drive: the output of the DC current-limiting amplifier. DC voltage.
When this pin is higher than 4.5 V or VS1, VS2, the current limit is activated: the voltage switch of the voltage triplet is lower than 1.5 V (charge pump circuit). They provide different voltage levels to external capacitors in order to pump the voltage from VDD to VCP.

application information
The UCC3750 provides complete control and protection of DC-DC converter operation, where Q1 passes through the function of a four-quadrant flyback converter for PWM signal and rectification by generating a ring signal for the telephone circuit. A typical AP-Q2, DR2 path to provide an application circuit with a 15 arbitrary loop generator shows an increasing positive reference voltage. This pulse width is controlled by the error amplifier output. As shown, the flyback converter takes a DC input (typically, the output is increased or decreased as directed by the associated 48V) and provides an isolated output. Before Q2/DR2, the maximum duty cycle is limited to 50% to pre-compressible frequency (and amplitude) AC signal vent DR1 is open.
Superimposed on the programmable DC offset. In mode 2, the reference voltage begins to drop, and the required path consists of the primary side PWM switch Q1, where the power is transferred back to the input. For this, when DR1 operates, it is necessary to adjust the return rectifier DR1, the four-winding transformer T1, the output mode, and the switch Q3. Rectifiers DR2 and DR3, synchronous/PWM switch Q2 as the rectifier return input. The UCC3750 has and q3, and the output filter cf. Resistor rsense provides the mode decoding circuit, which automatically guides the output current sensing of the protection circuit. PWM signal to q3, turn off q1. The different operating modes of the converter are described for AC power rectifier (PWM) switching. For the circuit and Figures 4a-4d, the equivalent CIR switching is shown.
CUITS in operating mode. Added q2, q3 1+–q1 q2
Primary diode contributes to true four-quadrant operation 2+–+q3(d1)
where both output voltage and power transfer can be 3–+q1 q3
bidirectional. Mode 1 is similar to the commonly used 4––q2(d1)

Application Information (continued)
When the reference signal changes from positive to negative - starts increasing towards zero, the power direction transitions from mode 2 to mode 3. In transmission, reversed again, in mode 4, q2 is pwmed. Mode 3, the converter acts again as DC-DC, it should be noted that in modes 2 and 3, when referring to the flyback converter (negative output). Similar to ENS mode, the phase of the feedback path is at -1 and Q1 is controlled by the PWM output, however, its recovery is vertical compared to the other two modes. The traditional tifying path is now through q3/dr3, as the PWM method of output polarity will cause instability since the characteristics are reversed. At the mode boundaries, there may be extremes. The UCC3750 separates out some distortion of the error signal that doesn't have much effect on THD or polarity, and determines the correct PWM signal, which is close to the zero-crossing point. Finally, as a reference signal, based on an independent mode determination circuit.

Application Information (continued)
The sine wave reference generator integrated circuit has a general low frequency sine wave reference generator with small harmonic distortion and high frequency accuracy. In the intended mode as shown in Figure 5, the reference generator will take its input from a 32kHz crystal (connected between XTAL1 and XTAL2) and generate a sine wave at 20Hz, 25Hz or 50Hz depending on the programming of pins fs0 and fs1. If you change the crystal frequency, the output frequency will change appropriately. A C-2 type quartz crystal is recommended (available from Epson through Digikey). If frequency accuracy is not a major issue, the more common, lower cost clock crystal (Type C) at 32.768kHz can be used with a smaller output frequency offset (20.5Hz instead of 20Hz). Additionally, the XTAL1 input can be output as a desired sine wave (divide by 1600, 1280 and 640 for different output frequencies). The sine wave output is centered around the 3V internal reference. Capacitor from sinref to gnd. Useful for smoothing sine wave references. The recommended value is at least 0.01 microF and a maximum of 0.1 microF. When both fs0 and fs1 are 1 (high), the sine reference is disabled and an external sine wave can be input to the sinref pin. This signal should have the same DC offset as the internal sine wave (3V). reference and error amplifier amplifiers. The DC reference voltage can vary over a wide range. Set to create an incorrect composite reference signal sine wave applied to the DC power supply. The recommended circuit connection for these circuits is zero for pure AC output, and in many common applications it is talk battery voltage (–48V). The UCC3750 accomplishes this task by summing the two signals weighted by resistors R14 and R15. The output of AMP1 also helps determine the mode of the circuit.

Application Information (continued)
The problem only occurs when the vb value is high (e.g. when ramping the signal, the op turns on the PWM signal 48V), and can be mitigated by using part of the re-fall below mag on the falling ramp, and re-falling as the vb input and re- Get the dc offset required for the offset end of the clock cycle. This technique can achieve synchronization with the resistance ratio. Immediately thereafter, the rectifier switch error amplifier is turned on to compare the reference signal with the PWM pulses that are turned off. The triangular nature ensures maximum duty cycle of the PWM by weighted summed output voltage at its reverse slope. enter. The error signal is further processed so that its output is 50%, providing an inherent current limit. Polarity and magnitude. The absolute value circuit (precise control logic and output SION full-wave rectifier) is used to obtain amplitude information, and the pulse width modulated signal is processed by the control logic. Polarity When used with a reference, consider the operating mode and output polarity signal polarity to determine the mode information. The ability to decide which output to modulate. The logic table absolute value circuit provides phase reversal when the ap- of the output is given in Table 2. For example, assume that Mode 2 and Mode 3 are appropriate to keep the reference signal properly looped in the first quadrant (positive gain polarity). At the same time the output of the error amplifier is also increasing). The output will lag the reference voltage by about 3V, and the full-wave rectified output (MAG) will be delayed by a certain delay, so the error amplifier output will be pos- converted to a signal above 3V. The signal is organized, resulting in sign=0. The logic table shows tangent to the oscillator ramp to generate the PWM output. GD1 is modulated at this stage, allowing the switching of the power oscillator and the PWM comparator to boost the output voltage to keep up with the UCC3750 having an internal oscillator capable of high reference voltages. Increasing the error (MAG) will result in higher frequency (>250kHz) operation. A resistor on the RT pin duty cycle that increases the output and captures the programming current to charge and discharge CT to reference. If the output is higher than that produces a triangular ramp waveform. Figure 7. Shows the reference (probably in the second quadrant, when the oscillator is connected to the circuit. Ramp peaks and valleys are reference drops), the flags change to 1 for 4.75V and 3V respectively. The nominal frequency is gd3, which reduces the output level by delivering power to the input. In the first and second quadrants, there may be some switching through zero. Some of this conversion can be eliminated when the reference slopes cross, advancing between modes through the PWM comparator and compensation components. Comparing the effects of error amplifier filtering and choice of compensation amplifier on the ramp waveform and error output. In the first quadrant, when the PWM operates the PWM signal. The PWM action is disabled and ON is applied to Q1, Q2 in rectifier mode by ramping the positive slope of the signal. Leading edge block - clock signal that allows the magnetic flux of the flyback transformer

reset (and transfer power to the output). Operation in quadrants 3 and 4 is symmetrical to the first two quadrants, where Q2 and Q3 are swapped. Note that the output signal of Q2 is logically inverted to allow driving the P-channel switch. An N-channel switch can also be used for Q2, but the drive circuit must be transformer isolated and polarity reversed. The outputs are designed for high peak current drive and low internal resistance. In an isolated system, GD1 must be coupled to Q1 using a gate drive transformer. DC Current Limit The DC current limit function provides short circuit protection by limiting the maximum current level and turning off the PWM function when the limit is reached. The DC limit is activated when the DC output is below 0.5 VCM or above 1.5 8226 ; VCM. The DC current limit is programmable via Setting: R5. =3.R6 At this ratio, a symmetrical DC limit with a threshold of ±0.5 V is obtained. For other ratios, the positive and negative voltage thresholds of the current-sense signal are given by (pos)=sense. Even in the second, current limit is applied to the active PWM and DCLIM, the UCC3750 will prevent switching at this point. For example, if q1 is a negative slope of the ramp, the PWM switch of q1 turns on the DC limit and operates in a loop.

priming pump and reference
The UCC3750 is designed to isolate the secondary side of a power supply. It requires a 5 volt power supply to operate on its ground pin. Note that the GND pin of the IC is also the reference point for the ring signal generated by the converter. If the converter output is in series with any other voltage, make sure that the available supply voltage is referenced to the converter output loop. The integrated circuit and its associated charge pump components such as generating all other voltages required by the system. The UCC3750 typically requires about 5mA to operate without any load on the drive output. The charge pump capacitor should be large enough to keep the VCP fairly stable while driving Q1-Q3 in the converter.