The CDC351 is a high performance clock driver circuit that distributes one input (A) to ten outputs (Y), minimizing clock distribution skew. The output enable (OE) input disables the output from entering a high impedance state. The CDC351 operates on a constant 3.3V VCC. Propagation delay is rounded up when using P0 and P1 pins. thefactoryadjustment ensures that part-to-part skew is minimized and kept within the specified window. P0 and P1 pins are not suitable for customer use and should be connected to GND.

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Low output skew, low pulse skew for clock distribution and clock generation applications

Operates at 3.3VV CC

LVTTL compatible inputs and outputs

Supports mixed mode signal operation (5V input and output voltage with 3.3VV CC)

Distribute one clock input to ten outputs

Distributed V and Ground Pins Reduce Switching Noise

High drive output (-32-mA I OH, 32-mA I OL)

State-of-the-art EPIC-IIB TM BiCMOS design significantly reduces power consumption

Package options include plastic small outline (DW) and reduced outline (DB) packages

logical symbols a.

Logic Diagram (Positive Logic)

Absolute Maximum Ratings

Exceeds free air temperature range for operation (unless otherwise stated)

(1) Supply voltage range, VCC - 0.5 V to 4.6 V. Input voltage range, VI

(2) - 0.5 V to 7 V. Voltage range applied to any output in VO

(3) - 0.5 V to 3.6 V. High state or power down state, current into any low state output, IO 64 mA input clamp current, IIK (VI < 0) - 18 mA output clamp current, IOK (VI < 0 ) - 50 mA package thermal resistance ΘJA

(4): DB package 147 °C/W. DW package 101°C/W. Storage temperature range, Tstg - 65°C to 150°C

Stresses beyond those listed under the Absolute Maximum Ratings "may cause permanent damage to the device. These are stress ratings only, and functional operation of the device under these or any other conditions, beyond the recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. If the input and output clamp current ratings are observed, the input and output negative voltage ratings may be exceeded. Package thermal resistance is calculated according to JESD51.

Recommended Operating Conditions (1)

VCC supply voltage 3 3.6 V

VIH high level input voltage 2 V.

VIL low level input voltage 0.8 V.

Input voltage 0 5.5 V.

IOH High Level Output Current - 32 mA

IOL low level output current 32 mA

fclock input clock frequency 100 MHz commercial 0 70°C

TA operating free air temperature

Industrial - 40 85°C

Voltage waveform

A. CL includes probe and fixture capacitance.

B. Waveform 1 is for outputs with an internal condition that causes the output to be low unless the output disables the control. Waveform 2 is used for outputs with internal conditions such that the output is high unless output control is disabled.

C. All input pulses are powered by a generator with the following characteristics: PRR≤10MHz, ZO=50Ω, tr≤2.5nsf≤2.5ns.

D. One measurement output per measurement, one measurement per measurement.

1-Line to 10-Line Clock Driver with 3-State Output

A. The output bias, tsk(o), is calculated as:

- Difference between fastest and slowest for tPLHn (n=1,2,3,4,5,6,7,8,9,10)

- Difference between fastest and slowest for tPHLn (n=1,2,3,4,5,6,7,8,9,10)

B. Pulse skew, tsk(p), calculated as the larger value of |tPLHn − tPHLn| (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10).

C. Handling skew, tsk(pr), calculated as:

- Difference between fastest and slowest tPLHn (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) under multiple devices with the same operating conditions

- Difference between fastest and slowest tPHLn (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) across multiple devices for the same operating conditions

Green: TI defines "green" to indicate that the content of chlorine (Cl) and bromine (Br) based flame retardants meets the threshold of JS709B low halogen requirement <= 1000ppm. Antimony trioxide-based flame retardants must also meet the threshold requirement of <= 1000ppm.

(3) MSL, peak temperature. - Moisture sensitivity rating according to JEDEC industry standard classification and peak solder temperature.

(4) There may be additional markings related to the logo on the equipment, batch tracking code information or environmental categories.

(5) Multiple device marks will be in brackets. Only one device token enclosed in parentheses, separated by "~", will be displayed on the device. If a line is indented, it is a continuation of the previous line and the combination of the two represents the entire device tag for that device.

(6) Lead/Ball Finish - Orderable equipment may have multiple material finish options. Completion options are separated by vertical grid lines. If done, lead/sphere paint values can wrap into two line values that exceed the maximum column width.