1 Function description
The VCA5807 is an integrated voltage-controlled 8-channel voltage-controlled amplifier designed specifically for ultrasound (VCA) – a programmable low noise amplifier (LNA) required for high performance, small form factor LNA, VCAT, PGA, LPF and CW mixing systems. The VCA5807 integrates a complete –24/18/12 dB gain time gain control (TGC) imaging path and continuous wave Doppler (CWD) path. It also has a –0.25/0.5/1 vpp linear input range. Users can select one of various power/noise –0.63/0.7/0.9 nv/rthz input-referred noise combinations to optimize system performance. – Programmable Active Termination So VCA5807 is a suitable ultrasonic analog front-end solution not only for high-end 40dB low noise voltage control systems, but also for portable systems. Attenuator (VCAT) The VCA5807 contains eight voltage channels 24/30 dB Programmable Gain Amplifier (PGA) Control Amplifier (VCA) and CW mixer. VCA 3rd Order Linear Phase Low Pass Filter (LPF) including Low Noise Amplifier (LNA), Voltage Controlled – 10, 15, 20, 30 MHz Attenuators (VCAT), Programmable Gain Amplifier – Butterworth (PGA) and Low Pass Filter (LPF). The LNA gain is programmable to support 250 mvpp to 1 vpp input noise/power optimized (full chain) signals. Programmable active termination is also 99 mw/ch at -0.75 nv/rthz, supported by the LNA. Ultra-low noise VCAT – 56 mW/ch at 1.1 nv/rthz with 40db attenuation control and improved overall low gain SNR – 80 mW/ch PGA for CW mode harmonic imaging and near field imaging Gain matching provides 24dB and 30dB gain options. At 5 dB (typ) and .05 dB (max) ADCs, one LPF can be configured for 10 MHz, 15 MHz, 20 MHz or 30 MHz to support ultrasonic low harmonic distortion applications at different frequencies. In addition, the fast and consistent overload recovery signal chain of the VCA5807 can handle low frequency sonar signal processing frequencies below 100 kHz, enabling it to be used not only in ultrasonic applications but also in passive mixers for continuous wave Doppler.
sonar application. (Continuous Working Days) – Low Closed Phase Noise – 156 dBc/Hz at 1. The VCA5807 integrates a low power passive mixer. kHz off the 2.5 MHz carrier and a low noise and amplifier to complete the onchipCWD beamformer. 16 selectable phase delays with a phase resolution of 1/16λ can be applied to each analog input signal. – Supports 32x, 16x, 8x, 4x, and 1x CW clocks, while supporting unique 3RD and 5th harmonics – 12dB rejection on 3RD and 5 Harmonic rejection filters are implemented for CW enhancement. sensitive. – Flexible Input Clock The VCA5807 is available in 14mm x 14mm, 100-14mm x 14mm, 100-pin TQFP. pin tqfp package, specified for operation from -40°C to 85C. Sonar Imaging Using Medical Ultrasound Imaging Non-destructive Evaluation Equipment

Such integrated circuits can be damaged by electrostatic discharge. Texas Instruments recommends the use of appropriate precautions. Failure to follow proper operation and installation procedures may result in damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits can be more susceptible to damage because very small parameter changes can cause the device to not meet its published specifications.

Serial Peripheral Interface (SPI) Operation Register Write Describes the different modes of programming can be done through the serial interface formed by pins sen (serial interface). enable), SCLK (serial interface clock), SData (serial interface data), and reset. All of these pins have pull-down resistors of 20kΩ to ground. When SEN is low, bit-to-device serial shifting is enabled. Serial data SData is latched on every rising edge of SCLK when SEN is active (low). Serial data is loaded into the register every 24 SCLK rising edges with SEN low. If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiple 24-bit words within a single active SEN pulse (there is an internal counter that counts groups of 24 clocks after the falling edge of sen). The interface can work with SCLK down from 20 MHz down to low speed (several Hz), even with non-50% duty cycle SCLK. The data is divided into two main parts: the register address (8 bits) and the data itself (16 bits), which is loaded into the address register. When writing to the register with unused bits, these should be set to 0
Note that reset must remain "1" for greater than 100 ns. After reset, more than 100 ns is recommended before writing to the SPI registers.

Register readout indicates that the device includes an option in which the contents of internal registers can be readout. This may be useful as a diagnostic test to verify serial interface communication between an external controller and the VCA. first, The bit (reg0[1]) needs to be set to "1". The user should then initiate a serial interface cycle specifying the address of the registers (A7-A0) whose contents must be read. The data bits are "don't care". The device will output the contents of the selected register (d15-d0) on the sdout pin. This starts from the falling edge of SCLK, and the typical delay T8 for SDOUT is 20 ns. For low-speed SCLK, SDOUT can be latched on the rising edge of SCLK. For high-speed SCLK, that is, SCLK period less than 60ns, it will best lock SDOUT on the next falling edge of SCLK. The timing diagram below shows this in action (the timing specification follows the same information provided. In read mode, the user still has access to through sdata/sclk/sen. To enable serial register writes, set

The VCA register map requires a reset process during the VCA5807 initialization phase. Initialization can be done in one of two ways:
1. With a hardware reset, a positive pulse is applied in the reset pin
2. The second step. By software reset, using the serial interface, by setting the software reset bit high. Setting this bit initializes the internal registers to their respective default values (all zeros), then self-reset software resets the bit low. In this case, the reset pin can be held low (inactive). After reset, all VCA registers are set to "0", which is the default setting. During register programming, all reserved/unlisted register bits need to be set to '0'. When the VCA5807 is in partial power down mode or full power down mode.

Register Description Input Impedance Configuration (active termination programmability) Different LNA input impedances can be accessed via Register 52[4:0]. The LNA input impedance is adjustable by creating and destroying feedback resistors between the LNA output and the ACTX PINS. Table 2 describes the relationship between LNA gain and 52[4:0] settings. The input impedance setting is the same as the input impedance setting.
TGC and CW paths.
In addition, the VCA5807 has 4 preset active termination impedances as described in 52[7:6]. Internal decoding is used to select appropriate resistors corresponding to different LNA gains.

Programmable Gain of CW Summing Amplifier Different gains can be configured for the CW summing amplifier through Register 54[4:0]. The gain is adjustable by enabling and disabling the feedback resistor between the summing amplifier input and output. This maximizes the dynamic range of the CW path. Sum the relationship between the amplifier gain and the 54[4:0] setting.

VCA5807 Overview The VCA5807 is an integrated voltage-controlled amplifier (VCA) solution specifically designed for ultrasound.
Systems requiring high performance and small size. The VCA5807 integrates a complete Time Gain Control (TGC) imaging path and Continuous Wave Doppler (CWD) path. It also allows the user to select various power/noise combinations to optimize system performance. The VCA5807 contains eight pass channels per channel including Low Noise Amplifier (LNA), Voltage Controlled Attenuator (VCAT), Programmable Gain Amplifier (PGA), Low Pass Filter (LPF) and CW mixer. In addition, several features in the VCA5807 are suitable for ultrasonic applications such as active termination, single channel control, fast power up/down response, programmable clamp voltage control, fast and continuous overload recovery, and turn-on. Therefore, the VCA5807 is an ultra-portable handheld system all the way to a high-end ultrasound system. Additionally, the VCA5807 can support sonar applications, considering its excellent low frequency (<100 kHz) response. Its simplified functional block diagram

Low Noise Amplifier (LNA) In many high gain systems, the LNA is the key to achieving overall performance. Using a new proprietary architecture, the LNA in the VCA5807 provides excellent low noise performance during operation. Quiescent current is very low compared to CMOS-based structures with similar noise performance. The Republic of India performs single-ended input to differential output voltage conversion. It can be configured with programmable gains of 24/18/12db and input referred noise of 0.63/0.70/0.9nv/√hz respectively. Programmable gain settings provide a flexible linear input range of up to 1vpp, fulfilling the new product requirements for high signal processing capabilities. Sensor Technology. Larger input signals can be accepted by the LNA, but the signal may be distorted. Because it exceeds the linear operating region of the LNA. Combined with low noise and high input range, the wide input enables dynamic range to support the high demands of various ultrasound imaging.
model.

The internal bias of the LNA input is approximately +2.4V; the signal source should be AC coupled to the LNA.
Input by appropriately sized capacitors, i.e., ≥ 0.1 µF. To achieve low DC offset drift, the VCA5807 integrates a DC offset correction circuit for each amplifier stage. To improve the overload recovery rate, an integrator circuit is used to extract the DC component of the LNA output, which is then fed back to the LNA supplemental input for DC offset correction. The DC offset correction circuit has a high-pass response and can be processed as a high-pass filter. The effective angular frequency is determined by the connected capacitor cBypass. The larger the capacitor in inm., the lower the corner frequency. For stable operating frequency when the highest HP filer is cut off, a capacitor ≥15nF can be selected. This angular frequency is almost the same as that of class C. For example, 15nf gives a corner frequency of about 100kHz, while 47nf gives an effective corner frequency of 33kHz. If low frequency operation is required, the DC offset correction circuit can also be disabled/enabled via register 52[12]. A large capacitor like 1 microF can be used to set the frequency of the low angle LNA DC offset correction circuit (<2 kHz)
frequency application.

The VCA5807 can be passively or actively terminated. In ultrasonic applications, active termination is preferred. Reduce mismatched reflections for better axial resolution without reducing noise figure. a lot of. Active termination values can be preset to 50, 100, 200, 400Ω; other values can also be programmed by the user via Register 52[4:0]. A feedback capacitor is required between the actx and the signal source as on the active termination path and a clamp circuit is also used to create a low impedance path.
When the VCA5807 sees an overload signal. The clamp circuit limits large input signals at the LNA input and improves the overload recovery performance of the VCA5807. The clamp can be set to 350mvpp, when register 52[10:9]=0, 600mVpp, 1.15Vpp automatically depends on the LNA gain setting. Other clamp voltages, such as 1.15Vpp, 0.6Vpp and 1.5Vpp, can also be achieved by setting Register 52[10:9]. This clamping circuit design also achieves good pulse inversion performance and reduces the effects of asymmetry. enter. Note that the clamp settings may change during LN gain switching. Therefore the clamping time of the clamp must be considered when adjusting the LNA gain, especially when the overload signal exceeds the clamping voltage.

The VCA5807 Low Noise Amplifier Voltage Controlled Attenuator with DC Offset Correction circuit is designed to have a linear In-dB attenuation characteristic, i.e. the average gain loss (in dB) is constant for each equal increment of the control voltage (VCNTL) , as follows: A differential control structure is used to reduce common-mode noise. A Simplified Attenuator The attenuator is essentially a variable voltage divider consisting of a series input resistor (RS) and seven parallel FETs, controlled by continuously activated clipping amplifiers (A1 to A7). VCNTL is a valid difference between vcntlp and vcntlm. Each clip amplifier can be understood as a dedicated voltage comparator with soft transfer characteristics and well-controlled output limit voltage. The reference voltages v1 to v7 are equally spaced in the 0V to 1.5V control voltage range. As the control voltage increases across the input range of each clipping amplifier, the amplifier output rises from the voltage.

When the FET is close to off, the fully on position is reached. The control voltage continues to rise as each FET approaches its on-state, and the next clipping amplifier/FET combination takes over. Part of the piecewise linear decay characteristic. Therefore, low control voltage has most FETs. Off, produces minimal signal attenuation. Likewise, high control voltages turn on the FETs, resulting in maximum signal attenuation. Therefore, each FET plays the role of reducing the shunt resistance of the voltage divider. Consists of RS and parallel FET networks. In addition, a digitally controlled TGC mode is implemented for better phase noise performance. VCA5807. The attenuator can be controlled digitally instead of analog by the control voltage VCNTL. This mode can be set by register bit 59[7]. The variable voltage divider is implemented as a fixed series resistor and FET. as a shunt resistor. Each FET can be turned on by connecting switches SW1-7. Opening each switch provides about 6dB of attenuation. This can be controlled by register bits 59[6:4]. This digital control function can eliminate noise in the VCNTL circuit, guaranteeing better signal-to-noise ratio and phase noise. For the TGC path.
Simplified Voltage Controlled Attenuator (Digital Architecture)

The noise of the voltage-controlled attenuator is monotonically related to the attenuation coefficient. At higher attenuation, the input-referred noise is higher and vice versa. Then, the noise of the attenuator is amplified by the PGA. becomes the noise floor at the ADC input. In the high attenuation operating range of the attenuator, where VCNTL is high, the input noise of the attenuator may exceed the output noise of the LNA; then the attenuator becomes the noise source that dominates the following PGA stage and ADC. Therefore, the noise of the attenuator should be minimized.
compared to LNA output noise. The attenuator of the VCA5807 is designed to achieve very low noise, even at high attenuation (low channel gain), with a better near-field signal-to-noise ratio. See PGA output configuration

Programmable Gain Amplifier (PGA)
After the voltage controlled attenuator, the programmable gain amplifier can be configured for 24db or 30db constant input referred noise of 1.75nv/rthz. The PGA structure consists of differential voltage-current. Converter with programmable gain, current clamp (bias control) circuit, with programmable low pass filter, and DC offset correction circuit. Its simplified block diagram is as follows: PGA simplified block diagram

Low input noise is preferred for PGAs whose noise contribution should not degrade the ADC's signal-to-noise ratio. after the attenuator. At minimum attenuation (for small input signals), lna noise dominates; at maximum attenuation (for large input signals), PGA and ADC noise dominate. Therefore, the 24dB gain of the PGA can achieve a better signal-to-noise ratio as long as the amplified signal can exceed the noise floor of the ADC. The PGA current clamp circuit (Register 51) can be enabled to increase VCA. If we measure the standard deviation of the output after overload, it is about 3.2 for 0.5 volts VCNTL. The LSB is under normal conditions, that is, the output settles within about 1 clock cycle after overload. With the current clamp disabled, the value is closer to 4 LSBs, meaning it takes longer before the output settles; however, with the current clamp enabled, the HD3 will degrade for PGA output levels >. -2dbfs. For example, for a –2dbfs output level, hd3 drops by about 3db. To maximize output dynamic range, the maximum PGA output level can exceed 2VPP (0 dbfs linear output range) with clamp circuitry. Therefore, an ADC with good overload recovery should be selected.
Note that in low and medium power modes, if the VCA5807 integrates an anti-aliasing filter in the form of a programmable low pass filter (LPF). Transimpedance amplifier. The LPF is designed as a differential, active, third-order filter with Butterworth. features and a typical 18dB per octave roll-off. Programmable via serial interface, the –1db frequency angle can be set to 10MHz, 15MHz, 20MHz and 30MHz. Filter bandwidth for all simultaneous channels.
In addition, an optional DC offset correction circuit is implemented. This correction circuit is similar to the one used in India. It extracts the DC component of the PGA output and feeds it back to the free input of the PGA DC offset correction. This DC offset correction circuit also has a high-pass response. The cutoff frequency is 80kHz. The DC offset correction circuit can be disabled if <80kHz operation is required. Via register 0x33[4].

CW Beamformer CW Doppler is a key feature of mid to high end ultrasound systems. In contrast to TGC mode, the CW path needs to handle high dynamic range and tight phase noise performance. Continuous Wave Beamforming is usually implemented in the analog domain due to the stringent requirements described above. Several beamforming methods are used in ultrasound systems, including passive delay lines, active mixers, and more. Passive mixer. Among them, the passive mixer realizes the optimization of power and noise. It meets the requirements of continuous wave processing, wide dynamic range, low phase noise, and accurate phase matching of gain.
A simplified CW path block diagram and an in-phase or quadrature (I/Q) channel block diagram are given. respectively below. Each CW channel includes a low-noise amplifier, a voltage-to-current converter, a switch-based mixer, a shared summing amplifier with low-pass filter and clock circuitry. All modules contain well-matched in-phase and quadrature channels for good image frequency rejection and beamforming accuracy. As a result, the image suppression ratio of the I/Q channel is better than the -46dbc required by the ultrasound system.

Note: The 10~15Ω resistance at CW amperage m/p is due to the internal IC wiring and may be slightly attenuated.
The CW mixers in the fully in-phase or quadrature-phase channel VCA5807 are passive switch-based mixers; passive mixers add less noise than active mixers. It gets good performance at low power consumption. The diagram and equation below describe the principle of the mixer. operation, where vi(t), vo(t), and lo(t) are the mixer’s input, output, and local oscillator (lo) signals, respectively. Lo(t) is square wave based and includes odd harmonic components as shown in the following equation: Block diagram of mixer operation According to the above equation, the 3rd and 5th harmonics of Lo can be connected with the 3rd and 5th harmonics. The harmonic signal in vi(t); or the noise around the 3rd and 5th harmonics in vi(t). Therefore, the performance of the mixer is reduced. In order to eliminate the side effects caused by square wave demodulation, AVCA5807 adopts a dedicated harmonic suppression circuit. The third and fifth harmonic components can be suppressed by more than 12 dB from the LO. Therefore, the lna output noise around the 3rd and 5th harmonic bands will not be down-converted to baseband. Therefore, a better noise figure is obtained. Conversion mixer loss is about -4db

The mixed current outputs of the 8 channels are summed internally. An internal low noise operational amplifier is used to convert the total current to a voltage output. The internal summing amplifier is designed for low power consumption, low noise and ease of use. The CW outputs of multiple VCA5807S can be further combined on the system board to realize a continuous beamformer with more than 8 channels.
The VCA5807 CW path supports multiple clocking options. Two CW clock inputs are required: N × _CW clock 1 × _cw clock, where _cw is the cw transmit frequency and n can be 32, 16, 8, 4, or 1. The user has the flexibility to choose the most convenient system clock solution for the VCA5807. In 32×_cw, 16×_cw and 8×_CW modes, the third and fifth harmonic suppression functions are supported. Therefore, the 16×_cw and 8×_cw modes achieve better performance than the 4×_cw and 1×_cw modes. 16×_cw and 32×_cw modes Compared with other modes, 16×_CW mode can achieve the best phase accuracy. It is the default mode operation of cw. In this mode, 16×_cw and 1×_cw clocks are required. 16×_CW produces 16 accurate LO signal stages. Multiple VCA5807s can be synchronized by 1×_cw, that is, the LO signals in multiple VCAs can be in the same startup phase. The phase noise specification is only critical for the 16x clock. The 1X clock is only used for synchronization and does not require low phase noise. See Phase Noise Requirements in CW Clock Selection. In addition, the 1X clock can be a continuous wave with a frequency of _cw, or a single pulse (1/16 x_cw) with a pulse width t>.
Each mixer is clocked through a 16x8 distribution crosspoint switch. The inputs to the crosspoint switch are 16 different phases of the 1X clock. It is recommended to align the rising edge of the 1x_cw and 16x_cw clocks. Crosspoint switches distribute clocks with appropriate phase delays to each mixer. For example, vi(t) is a received signal with a delay of 1/16 t and a delayed LO(t) should be applied to the blender to compensate for the 1/16 t delay. Therefore, a 22.5⁰ delay clock is chosen for this channel, which is 2π/16

Power, Ground, and Bypass Power and ground design plays an important role in mixed-signal system design. In most cases, it should be sufficient to lay out the printed circuit board (PCB) to use the single ground plane of the VCA5807. It should be noted that this ground plane is appropriately divided between the various parts within the system in order to minimize the interaction between the analog and digital circuits. In addition, opto-isolators or digital isolators such as ISO7240 can completely separate the analog part from the digital part. So they prevent digital noise from polluting the analog part. Table 10 lists the associated circuit blocks for each power supply.
Power supply and circuit block Power ground circuit block LNA, attenuator, PGA with fixture and BPF, reference circuit, CW AVDD (3.3VA) AVSS summing amplifier, CW mixer, VCA SPI company LNA, CW clock circuit, reference AVDD U 5V (5VA) AVSS CIRCUIT VCA5807 All bypasses and power supplies should be referenced to their corresponding ground planes. All power pins should be bypassed with 0.1µF ceramic chip capacitors (size 0603 or smaller). To minimize lead and trace inductance, capacitors should be placed as close to the power pins as possible. These capacitors are best placed directly on the package if double-sided components are allowed. Additionally, larger bipolar decoupling capacitors (2.2µF to 10µF, effective at lower frequencies) can also be used for the mains pins. These components can be placed on a nearby printed circuit board (<0.5" or 12.7" mm) to the VCA5807 itself. The VCA5807 has many reference supplies that need to be bypassed, such as CM-BYP, VHIGH, and Vref_-in. These pins should be bypassed by at least 1µF; high value capacitors can be used for better low frequencies. Noise suppression. For best results, choose a low-inductance ceramic chip capacitor (size 0402, >1 microF) and place it as close to the device pins as possible.
High-speed mixed-signal devices are sensitive to various noise couplings. A major source of noise is switching noise from serializers and output buffers/drivers. For the VCA5807, care has been taken to ensure that the interaction between analog and digital power supplies within the device is kept to a minimum. quantity. The amount of noise coupled and transmitted by the digital and analog sections depends on the effective inductance of each power and ground connection. The lower effective inductance of the power supply and the ground pin improve noise rejection. Therefore, multiple pins are used to connect each pin supply and ground. It is important to maintain low inductance characteristics throughout the design of the printed circuit board. Layout with appropriate planes and layer thicknesses.
Board layout Proper grounding and bypassing, short lead lengths, and the use of ground and power planes are especially important for high-frequency designs. Achieving the best performance with high performance A device like the VCA5807 requires careful attention to the layout of the printed circuit board to minimize board effects. Parasitic and optimized component placement. Multilayer printed circuit boards generally ensure the best results and allow for easy component placement.
Additionally, proper delay matching of the CW clock path should be considered, especially with high channel counts. For example, a phase error of 22.5°C may exist if the clock delay is half of 16 times the clock period. Therefore, the timing delay difference between channels contributes to the accuracy of the beamformer. To avoid noise coupling through the power supply pins, it is recommended to keep sensitive input pins such as INM, INP, ACT pins always from the AVDD 3.3 V and AVDD 5 V planes. For example, traces or vias connected to these pins should not pass through the AVDD 3.3 V and AVDD 5 V planes.