The ADS805 is a 20MHz, high dynamic range, 12-bit pipeline analog-to-digital converter ADC. The converter includes a high bandwidth track and hold, providing excellent spurious performance that meets and exceeds the Nyquist rate. This high bandwidth, linear sample-and-hold function minimizes harmonics and has low jitter for excellent signal-to-noise ratio (SNR) performance. The ADS805 is also pin compatible with the 10MHz ADS804 and 5MHz ADS803.

ADS805 provides internal reference or external reference can use reference. The ADS805 can be programmed with a 2Vp-p input range, a single drive is the easiest op amp and provides the best spurious performance. Alternatively, a 5Vp-p input range can be used for the lowest output range

Input referred noise is 0.09LSBs rms for excellent imaging performance. The input range can also be set between 2Vp-p and 5Vp-p, single-ended or differential. The ADS805 also provides an overrange flag to indicate when the input signal exceeds the full-scale range of the converter. This flag can also be used to reduce the gain of the front-end signal conditioning circuit.

The ADS805 uses digital error technology to provide excellent differential linearity for demanding communications, medical imaging, video and test instrumentation applications where its low distortion and high SNR provide additional headroom. The ADS805 is available in an SSOP-28 package.

feature

HIGH SFDR: 74dB at 9.8MHz fIN

High SNR: 68dB

Low power: 300mW

LOW DLE: 0.25LSB

Flexible input range

Out of range indicator

application

STUDIO CAMERAS

IF and BASEBAND digitization

COPIERS

test instrument

Application Information

drive analog input

The ADS805 allows driving its analog inputs single-ended or differential. The focus of the discussion below is on single-ended configurations. Often, it is easier to implement, and the ADS805's specified specifications are characterized using a single-ended mode of operation. AC-COUPLEDINPUTCONFIGURATION

The interface configuration of the most common circuit example DS805 is given in Figure 1 below. Use the VREF pin to connect to the SEL pin to define a full-scale input range of 2Vp-p. This signal is AC coupled single-ended using a low distortion voltage feedback to the ADS805 amplifier OPA642 . Often required for single-supply components, running the ADS805 with full-scale input signal swings requires level shifting of the amplifier zero to center the analog signal to meet the ADC's input range requirements. Using a DC blocking capacitor between the driver's output and the converter's input, a simple level-shifting scheme can be implemented. In this configuration, the top and bottom references (REFT, REFB) provide output voltages of +3V and +2V, respectively. Here, two resistor pairs (2 8226 ; 2kΩ) are used to create

The common mode voltage is about +2.5V to bias the ADS805 (IN, IN) inputs to the desired DC voltage. One advantage of AC coupling is that the drive amplifier still exists to operate with a ground signal swing. This will keep the best possible distortion performance since the signal swing is kept within the linear region of the op amp to maintain sufficient supply track space. Consider using an inverting gain configuration to eliminate CMR-induced amplifier errors. Adding a small series resistor (RS) at the output of the op amp and the input of the ADS805 can be used in almost any interface configuration. This will decouple the op amp's output capacitive load and avoid gain peaking, which can cause

Increased noise. For best spurious and distortion performance, resistor values should be kept below 100Ω. Additionally, the series resistor, along with the 100pF capacitor, creates a passive low-pass filter that limits the bandwidth to broadband noise, thereby helping to improve signal-to-noise performance. The DC-COUPLED does not have a horizontal shift. In some applications, the analog input signal may already be biased to match the level of the selected input ADS805's range and reference level. In this case, it is only necessary to provide a sufficiently low source impedance for the selected input IN or IN. Always consider broadband op amps as their output impedance will remain below a wide frequency range. DC - Coupled with horizontal shift Several applications may require a bandwidth signal path including DC, in which case the signal must be DC coupled to the ADC. To achieve this, the interface circuit must provide DC level shifting. Circuit Introduction Figure 2 below uses a single-supply, current-feedback operational amplifier, the OPA681 (A1), with a ground-centered input signal and the DC offset required to add a. The ADS805 typically uses a common-mode voltage of +2.5V, established by resistors R3 and R4, and connected to the IN input of the converter. Amplifier A1 operates in an inverting configuration. Here, resistors R1 and R2 set the DC bias level of A1. Because the operation assumes RF = RIN, DC offset, the noise gain of the amplifier is +2V/V. The voltage applied to its non-inverting input must be split to +1.25V, resulting in a DC output voltage of +2.5V. The voltage difference between the IN and IN inputs of the DC input ADS805 effectively creates an offset that can be corrected by adjusting the values of resistors R1 and R2. The op amp's bias current may also cause undesired conditions

Selection criteria for an appropriate op amp should include input bias current, output voltage swing, distortion, and noise specifications. Note that overall the signal phase is reversed in this example. The original signal polarity is re-established, the IN and IN connections are always interchangeable. Single-ended to differential configuration (TRANSFORMER-COUPLED) In order to select the most suitable interface circuit ADS805 performance requirements must be known. If a particular application requires an AC-coupled input the next step is to determine the method of application signal; single-ended or differential. The differential input is based on the fact that the configuration can provide significant advantages to achieve good SFDR performance. In differential mode, the signal swing can be reduced to half the swing required for single-ended drive. Second, by driving the ADS805 differentially, the even harmonics will be reduced. The figure below shows the schematic for the proposed transformer-coupled interface circuit. Resistors across the secondary side (RT) should be set to obtain input impedance matching (eg, RT = n2 RG). An example of an application that would benefit from a differential input configuration is the digitization of IF signals. The wide sample-and-hold input bandwidth makes the ADS805 well suited for narrowband and wideband IF downconversion applications. The ADS805 maintains excellent dynamic performance over multiple Nyquist zones, covering a wide range of IF frequencies (see Typical Characteristics). Using the ADS805 for direct IF conversion eliminates the need for analog mixers and subsequent functions and filters such as amplifiers, reducing system cost and complexity.

Reference operation

The ADS805 integrates a bandgap reference circuit including logic outputs that provide a +1V or +2.5V reference by simply selecting the appropriate pinband configuration. Different reference voltages can be generated using two external resistors, which will set the gain of the different internal reference buffers. For greater design flexibility, the reference voltage used by the internal reference and external reference can be turned off. The table below provides an overview of the possible reference options and pin configurations.

A simple model of the internal reference circuit is shown in the figure below. The internal blocks are a 1V bandgap voltage reference, a buffer, a resistor reference ladder and the necessary currents for the driver internal nodes that provide top and bottom references. The output of the buffer appears on the VREF pin as shown. The input range of the full ADS805 is determined by the voltage at VREF, according to Equation 1: Full-scale input range = 2 VREF(1) Note that the current drive capability of this amplifier is limited to about 1mA and should not be used to drive low level loads . The programmable reference circuit is determined by the voltage applied to the select pin (SEL). The top reference (REFT) and bottom reference (REFB) are mainly used for external bypass. For proper operation of all reference configurations, it is necessary to provide robust bypassing of the reference pins to minimize clock feedthrough. Figure 2 below shows the proposed decoupling network. Additionally, the common-mode voltage (CMV) can be used as a reference level to provide an appropriate offset drive circuit. However, care must be taken not to significantly load this node, which is unbuffered and has high performance impedance. Another way to generate a common-mode voltage is shown in Figure 6. Here, two external precision resistors (with a 1% tolerance or better) are placed between the top and bottom reference pins. The common mode level will appear at the midpoint. The output buffers of the top and bottom reference are designed to supply approximately 2mA of current, output current.

It is recommended to refer to the bypass scheme.

Alternative circuits for generating common-mode voltages.

Equivalent reference circuit.