Pin description
The SPI chip select (/cs) pin enables and disables device operation. When /cs is high, the device is deselected and the serial data output (DO or IO0, IO1, IO2, IO3) pins are in high impedance. when? Deselected unless an internal erase, program or write status register cycle is in progress. When /cs goes low, the device will be selected, power consumption will increase to the active level, and instructions can write to and read data from the device. After power up, /cs must transition from high to low to accept new commands. The /cs input must track the VCC supply level on power up and power down. This can be done using a pull-up resistor on the /cs pin if desired.
Serial data input, output and IOS (DI, DO and IO0, IO1, IO2, IO3) The W25Q128FV supports standard SPI, dual SPI and quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write commands, addresses, or data to the rising edge of the serial clock (CLK) input pin on the device. Standard SPI also uses a unidirectional do (output) to read data or status from the device on the falling edge of CLK. Dual and quad SPI instructions use the bidirectional IO pins to serially write commands, addresses, or send data to the device on the rising edge of CLK, and read data or status from the device on the falling edge of CLK. CLK. The Quad SPI instruction requires setting the nonvolatile Quad Enable bit (QE) in Status Register 2. When qe=1, the /wp pin becomes io2 and the /hold pin becomes io3.
The write protect (/wp) pin can be used to prevent writing to the status register. The block protection (cmp, sec, tb, bp2, bp1, and bp0) bits used in conjunction with the status register and the status register protection (SRP) bit, a 4KB sector, or a portion of the entire memory array can be hardware protected. The /wp pin is active low. When the qe bit of the status register-2 is set to quad input/output, the wp pin function is not available because this pin is used for io2. Configuration for quad I/O operation.
The hold pin allows the device to be suspended when it is actively selected. When / is held low, when /cs is low, the do pin will be at high impedance and the signals on the DI and CLK pins will be ignored. When / is held high, device operation can resume. The /hold function can be useful when multiple devices share the same SPI signal. The /HOLD pin is active low. When the QE bit of the status register-2 is set to quad I/O, the /HOLD pin function is not available, because this pin is used for IO3 serial clock (CLK) SPI serial clock input (CLK) pin is serial Input and output operations provide timing. (See SPI Operation.) Reset (/reset) The reset pin allows the controller to reset the device. For 8-pin package, when qe=0, IO3 can configure the pin as a/hold pin or a/reset pin according to the status register setting. When qe=1, the /hold or /reset functions do not work with 8-pin configurations. Packaged on a 16-pin SOIC, a dedicated/reset pin is provided, independent of the QE bit setting.

Standard SPI Description
The W25Q128FV is accessed via an SPI-compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (CS), Serial Data In (DI), and Serial Data Out (DO). Standard SPI instructions use the rising edge of the DI input to serially write commands, addresses, or data to the device. CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK. SPI bus operating modes 0 (0,0) and 3 (1,1) are supported. Mode 0 and Mode 3 relate to when the SPI bus master is in standby and data is not transferred to the serial flash. For Mode 0, the CLK signal is typically low on falling and rising edges of /cs. For Mode 3, the CLK signal is normally high on the falling and rising edges of /cs.
Dual SPI Instructions The W25Q128FV supports dual SPI operation when using instructions such as "Fast Read Dual Output". (3BH) and "Fast Read Dual I/O (BBH)". These instructions allow data to be transferred to the device at two to three times the rate of normal serial flash devices. Dual SPI read instructions are ideal for quickly downloading code to RAM at power up (code shadowing), or executing non-speed critical code directly from the SPI bus (XIP). When using dual SPI commands, the DI and DO pins become bidirectional I/O pins: IO0 and IO1.

Four SPI instructions W25Q128FV supports Quad SPI operation (6Bh) Fast Read Quad Input/Output (EBH) Word Read Quad Input/Output (E7H) when using instructions such as "Fast Read Quad Output" " and "Octal Word Read Quad Input/Output" (e3h). These instructions allow data to be transferred to or from the device at rates that are normal serial flash. The quad read instructions operate at both sequential and random access transfer rates, allowing fast Code-behind to RAM or executed directly from the SPI bus (XIX). When four SPI instructions are used, the DI and DO pins become bidirectional IO0 and IO1, and the /wp and /hold pins become io2 and io3, respectively. Four Each SPI instruction requires the non-volatile Quaternary Enable bit (QE) in Status Register-2 to be set.
QPI description
The w25q128fv supports Quad Peripheral Interface (qpi) operation only when switching between devices. Use the "enter qpi(38h)" command to switch from standard/dual/quad SPI mode to QPI mode. A typical SPI protocol requires byte-long instruction codes to be shifted into the device only through the 8 DI pins. serial clock. QPI mode utilizes all four IO pins to input instruction codes, so only two serials need clocking. This can significantly reduce SPI instruction overhead and improve system performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusives. Only one mode can be active at any given time. The "enter qpi(38h)" and "exit qpi(ffh)" commands are used to switch between these two modes. After power-up or software reset using the "reset(99h)" command, the default state of the device is standard/dual/quad SPI mode. To enable QPI mode, the non-volatile requires the Quaternary Enable bit (QE) in Status Register-2 to be set. When using QPI instruction, whether DI and pins become bidirectional IO0 and IO1, /wp and /hold pins become IO2 and IO3 hold function For standard SPI and dual SPI operation, the /hold signal allows W25Q128FV to operate in active select Pause when /cs is low. The /hold function may be useful in situations where SPI data and clock signals are shared with other devices. For example, consider that the page buffer is only partially written when priority interrupts need to use the SPI bus. In this case, the /hold function can save the state of the instruction and data in a buffer so that the bus stops as soon as it becomes free. The /hold function is only available for standard SPI and dual SPI operation, not during Quad SPI or QPI. The quaternary enable bit qe in Status Register-2 is used to determine whether the pin is used as/retained as a pin or as a data I/O pin. When qe=0 (factory default value), the pin is /hold, when qe=1, the pin will become an I/O pin, and the /hold function is no longer available.
To initiate the A/HOLD condition, the device must be selected with /CS low. The A/HOLD condition will activate ON the falling edge of the ON/HOLD signal if the CLK signal is already low. If CLK is not already low,/after the next falling edge of CLK, the hold state will be active. The /hold condition will be on the rising edge of the display/hold signal if the CLK signal is already low. If CLK has not fallen yet / the hold condition will terminate after the next falling edge of CLK. In the A/HOLD state, the serial data output (do) is high impedance, and the serial data input (di) and serial clock (clk) are ignored. The chip select (/cs) signal should remain active (low) for the entire duration of the /hold operation to avoid resetting the device's internal logic state.

Software reset and hardware/reset pins
The W25Q128FV can be reset to its initial power-on state by a software reset sequence (any sequence in SPI). mode or QPI mode. This sequence must include two consecutive commands: enable reset (66h) & reset (99h). If the command sequence is successfully accepted, the device will take about 30us. (TRST) reset. No commands are accepted during reset. For wson-8 and tfbga packet types, the w25q128fv can also be configured to use a hardware/reset pin. The hold/rst bits in Status Register 3 are configuration bits for the /hold pin function, or reset pin function. When hold/rst=0 (factory default), the pin will act as the described A/hold pin. Above; when hold/rst=1, the pin acts as a /reset pin. Drive/reset pin to lower position for at least some time. ~1us (treset*) resets the device to its initial power-on state. Any ongoing program/erase operations will be interrupted and data corruption may occur. When /reset is low, the device will not accept any command input.
If the QE bit is set to 1, the /hold or /reset function will be disabled and the pin will be one of four. Data I/O pins.
For the SOIC-16 package, the W25Q128FV provides a dedicated /reset pin in addition to /hold (IO3). pins, as shown in Figure 1b. Pulling the /reset pin low for at least 1us (treset*) will reset. The initial power-on state of the device. The hold/rst bits or the qe bits in the status register do not affect the functionality of this dedicated/reset pin. The hardware/reset pin has the highest priority of all input signals. Driving/resetting low for a minimum time of ~1us (treset*) will interrupt any ongoing external/internal operations, regardless of the state of other SPI signals (/cs, clk, ios, /wp and/or /hold). NOTE: While faster/reset pulses (as short as a few hundred nanoseconds) will usually reset the device, at least 1US is recommended to ensure reliable operation.

Write-protecting applications that use non-volatile memory must account for noise and other adverse system conditions that can compromise data integrity. To solve this problem, the W25Q128FV offers several methods to protect data from accidental writes.
Write Protection Features • Device reset when VCC falls below threshold • Delayed write disable after power up • Write enable/disable instruction and automatic write disable after erase or program • Software and hardware using status register (/wp pin) Write protection • Additional separate block/sector lock for array protection • Write protection using power down command • Write protection that locks status registers until next power up • One-time program (OTP) using array of status registers and security registers ) write protection*
When powered on or off, the W25Q128FV will be below the threshold of VWI at VCC. On reset, all operations are disabled and commands are not recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of TPUW. This includes Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register commands. Note that the chip select pin (/cs) must track the VCC supply level at power-up until the VCC minimum level and TVL delay is reached, and must also track the VCC supply level at power-down to prevent unfavorable command sequences. This can be done using pull-up resistors/cs if desired.
After power-up, the device is automatically in a write-disabled state with the Status Register Write Enable Latch (WEL) set to 0. The write enable command must be issued before the page program, sector. Erase, Block Erase, Chip Erase or Write Status Register commands are accepted. The write-enable latch (WEL) will automatically clear to a write-disabled state of 0 upon completion of a program, erase, or write instruction. Use the Write Status Register instruction and set the Status Register Protection (srp0, srp1) and Block Protection (cmp, sec, tb, bp[2:0]) bits. These settings allow part or the entire memory array to be configured as read-only. In combination with the write-protect (/wp) pin, changes to the status register can be enabled or disabled in hardware. control. See the Status Registration section for more information. In addition, the power down command provides an additional level of write protection because all commands except to release the power off are ignored.
illustrate.
The W25Q128FV also provides another method of write protection using separate block locks. Each 64kb block (except top and bottom blocks, total 510 blocks), each 4kb sector top/bottom block (32 sectors total) is equipped with a separate block lock bit. When the lock bit is 0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1, erase or program commands issued to the corresponding sector or block will be ignored. When the device is powered up, all individual block lock bits will be 1, so the entire memory array is protected from erasing/programming. The "Single Block Unlock (39H)" command must be issued to unlock any particular sector. or block. The wps bits in Status Register 3 are used to decide which write protection scheme should be used. when? wps=0 (factory default), the device will use only cmp, sec, tb, bp[2:0] bits to protect the array; when wps=1, the device will use a separate block lock for write protection.

Status and Configuration Registers
The W25Q128FV provides three status and configuration registers. Read Status Registers - 1/2/3 commands can be used to provide flash array availability status whether device write enabled or disabled, write protection status, quad SPI settings, security register lock status, erase/program suspend status, output drive strength , power up and current address mode. Write Status Register commands can be used to configure the device write protection function, quad SPI settings, security register OTP lock, hold/reset function, output driver strength and power-on address mode. Write access to the Status Register is controlled by the state of the nonvolatile Status Register Protection bits. (srp0, srp1), write enable command, /wp pin during standard/dual SPI operation.
Status Register Erase/Write in Progress (Busy) - Only Status Busy is a read-only bit in the Status Register (S0), when the device executes Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase , Write Status Register or Erase/Program Security Register instructions. During this time, the device will ignore further instructions except Read Status Register and Erase/Program Suspend instructions (see tw, tpp, tse, tbe and TCE in AC Characteristics). When a program, erase or write status/secure register instruction is complete, the busy bit will be cleared to a 0 state, indicating that the device is ready to accept further instructions. Write Enable Latch (WEL) - Status Only The Write Enable Latch (WEL) is a read-only bit in the Status Register (S1) that executes the Write Enable instruction. When the device is write disabled, the WEL status bit is cleared to 0. Disabled state occurs at power-up or after any of the following commands: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register, and Program Security register.

Block Protection Bits (bp2, bp1, bp0) - Volatile/Non-volatile Writable Block Protection Bits (BP2, BP1, BP0) are status registers (S4, S3, and s2) that provide write protection control and status. The Write Status Set Block Protection Bits Register instruction can be used (see tw in AC Characteristics). All, all or part of the memory array can be protected by program and erase instructions (see Status Register Memory Protection Table). The factory default setting for this block protection bit is 0, with no array protection.

Erase/Program Suspend Status (SUS) – Status Suspend Status Only Bits are read-only bits in the Status Register (s15) during the execution of the Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by erase/program restore.
(7ah) command and power down and power cycle.
Secure Register Lock Bits (lb3, lb2, lb1) – Volatile/Non-Volatile OTP Writable Secure Register Lock Bits (lb3, lb2, lb1) are non-volatile one-time program (otp) bits that are in state. Registers that provide write protection control and status for secure registers (s13, s12, s11). The default state of this LB3-1 is 0 and the security registers are unlocked. The Write Status Register instruction can be used. LB3-1 is one-time programmable (OTP), once set to 1, the corresponding 256-byte security register will permanently become read-only.
Quaternary Enable (QE) – Volatile/Non-Volatile Writable Quaternary Enable (QE) bit is a non-volatile read/write bit in the Status Register (S9) that allows Quaternary SPI as well as QPI operation. When the QE bit is set to the 0 state (factory default), the /wp pin and /hold are enabled. When the QE bit is set to 1, the four IO2 and IO3 pins are enabled and the /wp and /hold functions are disabled.

The QE bit must be set to 1 before issuing "enter qpi(38h)" to switch devices. Standard /dual/quad spi to qpi, otherwise the command will be ignored. When the device is in qpi mode, the QE bit will remain 1. The "Write Status Register" command in qpi mode does not work from Warning: If the /wp or /hold pins are in standard SPI or dual SPI operation, the QE bit should not be set to 1.

Write Protection Select (WPS) – The volatile/non-volatile writable WPS bits are used to select which write protection scheme should be used. When wps=0, the device will use a combination of cmp, sec, tb, bp[2:0] bits to protect specific regions of the memory array. when? wps=1, the device will use a single block lock to protect any single sector or block. The default value of this all individual block lock bits is 1 after a device power-up or reset.
Output Driver Strength (DRv1, DRv0) – The volatile/nonvolatile writable DRv1 and DRv0 bits are used to determine the output driver strength for read operations. /hold or /reset pin function (hold/rst) – The volatile/non-volatile writable hold/rst bit is used to determine if the hardware pin should be used for the 8-pin package. When hold/rst=0 (factory default), the pin acts as /hold; when hold/rst=1, the pin acts as /reset. However, the /hold or /reset functions are only available at QE=0. If QE is set to 1, the /hold and /reset functions are disabled and the pins will be used as dedicated data. I/O pins.
Reserved Bits - Non-Functions There are some reserved status register bits that can be read as "0" or "1". It is recommended to ignore the value of these bits. During the "Write Status Register" instruction, reserved bits can be written to "0", but have no effect.

illustrate
The standard/dual/quad SPI instruction set of the W25Q128FV includes 45 basic instructions for full control over the SPI bus to issue commands when falling chip edge select (/cs). The first byte of data clocked into the DI input provides the instruction code. Data at the DI input is sampled first on the rising edge of the clock, most significant bit (MSB). The qpi instruction set of the w25q128fv consists of 32 fully controlled basic instructions. Commands via the SPI bus are initiated by the falling edge of the chip.
select (/cs). The instruction code is provided through the first data byte of the IO[3:0] pins. All data is sampled on the rising edge of the clock on the four IO pins, most significant bit (MSB) first. All QPI instructions, address, data and dummy bytes use all four IO pins to transfer data per byte every two serial clocks (CLK). The length of the instruction varies from one byte to several bytes, which may be followed by address bytes and data. bytes, dummy bytes (don't care), and in some cases a combination. Use complete instructions edge rising edge/cs.
Any read instruction can be completed after any clock bit. However, all instructions writing, programming or erasing must be done on byte boundaries (driven by /cs after the full 8 bits). Otherwise the directive will be ignored. This feature further protects the device from accidental writes. In addition, when the memory is being programmed or erased, or when the status register is being written, all instructions other than read the status register are ignored until programmed or erased.
The cycle is complete.

Write Status Register-1 (01H), Status Register-2 (31H), and Status Register-3 (11H) The Write Status Register instruction allows writing to the Status Register. Writable status register bits include: srp0, sec, tb, bp[2:0] in status register-1; cmp, lb[3:1], qe, srp1 in status. Register 2; Hold/Reset in Status Register 3, DRV1, DRV0, WPS and ADP. All other status register bit positions are read-only and will not be affected by write status register instructions. lb[3:1] are non-volatile OTP bits, once set to 1, they cannot be cleared to 0. To write to nonvolatile status register bits, the standard write enable (06H) command must be preceded by a write status register command executed for the device to accept (status register bit WEL must be equal to 1). Once writing is enabled, enter the command by driving /cs low, send the command code "01H/31H/11H", and then write the status register data byte, to write the volatile status register bit, it must be in the volatile state The register (50h) instruction enable write has been performed before the write status register instruction (status register bit WEL remains at 0). However, SRP1 and LB[3:1] cannot be changed from "1" to "0" because of their OTP protection bits. When power is turned off or a software/hardware reset is performed, the volatile status register bit values are lost and the nonvolatile status register bit values are restored. During a non-volatile status register write operation (06h combined with 01h/31h/11h), after driving /cs high, a self-timed write status register cycle will begin for a duration of tw. While a write status register cycle is in progress, the read status register instruction can still be accessed to check the status of the busy bit. In the write state, the busy bit is 1. Register the loop and 0 when the loop is complete and ready to accept other instructions again. After the Write Status Register cycle has completed, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.