Features

Field effect transistor input amplifier

1 PA input bias current

Low cost

High -speed: 145 MHz, 3 DB bandwidth (G u003d+1)

180 V/μs conversion rate (g u003d+2)

Low noise

7 nv/√Hz (f u003d 10 10 kHz)

0.6 FA/√ Hertz (f u003d 10 kilow)

Wide power supply voltage range: 5 V to 24 v

Single power supply and rail pairing [ 123]

The maximum offset voltage is 1.5 MV

High -common model suppression ratio: 100 db

excellent deformation specification

sfdr 88 db@1 MMH

Low power: 6.4 MA/amplifier Typical power current

No phase reversal

Small packaging: SOIC-8, SOT-23-5, and MSOP

Application

Instrument instrument

Optical diode front placement large

Filter

A/D drive

[123 ] Horizontal displacement

Cushion

General description

AD8065/AD8066 FastFET amplifier is a voltage feedback amplifier, FET input provides high performance and ease of use. AD8065 is a single player, and AD8066 is a dual amplifier. These amplifiers are developed in the Analog Devices, Inc. Private XFCB process, allowing extremely low noise operations (7.0 nv/√Hz and 0.6 FA/√Hz) and very high input impedance.

AD8065/AD8066 has a width power supply range from 5V to 24V, which can work on a single power supply. The bandwidth is 145MHz and is designed for multiple applications. In order to increase the multifunctionaltability, the amplifier also contains rail transition.

Despite the low cost, the amplifier provides excellent overall performance. Differential gains and phase errors are 0.02%and 0.02 °, respectively, plus 0.1DB of flatness to 7MHz, making these amplifiers ideal for video applications. In addition, they also provide high conversion rates of 180 V/μs, excellent distortion (SFDR is 88 db@1 mHz), extremely high co -mode suppression 100 dB, and under preheating conditions Maximum 1.5 mV's low input offset voltage. AD8065/AD8066 only uses a typical power current of 6.4 MA/amplifier for operation, and can provide a load current of up to 30 mA.

AD8065/AD8066 is a high-performance, high-speed, small-package FET input amplifier: SOIC-8, MSOP-8 and SOT-23-5. Their rated operating temperature range is 40 ° C to+85 ° C.

Connection Figure

Maximum power consumption

AD8065/AD8066's maximum secure power consumption was warm by chip head ( TJ) related rising restrictions. The plastic of the packaging mold will reach the partial temperature. Under about 150 ° C (ie glass temperature), plastic will change its performance. Even if this temperature limit is temporarily exceeded, the stress of the packaging of the packaging on the mold will be changed permanently, and the parameter performance of the AD8065/AD8066 is permanently changed. The knot temperature that exceeds 175 ° C for a long time can cause changes in silicon devices and may cause failure. The static air thermal characteristics (θJa), ambient temperature (TA), and total power (PD) in the package determine the chip temperature. The knot temperature can be calculated as:

The power consumption (PD) in the package is the sum of all output power consumed by static power consumption and packaging in the package. Static power is the voltage (VS) between the power pins (VS) by static current (IS). Assuming the load (RL) refers to the confession, the total driver power is vs/2 × iOUT, one of which is scattered in the package, and the other is dissipated in the load (vout × iOUT). The difference between the total driver and the load power is the driving power consumed in the package.

The RMS output voltage should be considered. If RL refers to vs if in a single power supply, the total driver power is vs × iOUT.

If the RMS signal level is uncertain, consider the worst case, when the Vout u003d vs/4 from RL to Midsupply.

In the single power operation of RL reference vs , the worst case is VOUT u003d vs/2.

The airflow will increase heat dissipation and effectively reduce θJa. In addition, more metals are directly exposed to the packaging wires, which will reduce θJa from metal traces, holes, grounding, and power planes. As described in section a section of layout, grounding, and bypassing, it is necessary to be careful to minimize the parasitic capacitance of the high -speed computing amplifier input.

FIG. 3 shows SO on the JEDEC standard 4 layer boardIC (125 ° C/W), SOT-23 (180 ° C/W), and MSOP (150 ° C/W) maximum safe power consumption. The value of θJa is approximate.

Short -circuit of output

The output of AD8065/AD8066 can cause disaster failure at a short -circuit or large current consumption of the ground or excessive current consumption.

Typical performance features

Default conditions: ± 5 V, CL u003d 5 PF, RL u003d 1 K , Vout u003d 2 V p-P, temperature u003d 25 ° C.

] Test circuit SOIC-8 Point Operating theory

] AD8065/AD8066 is a voltage feedback computing amplifier. It combines laser minimum JFET input levels with super fast complementary bipolar (XFCB) process to achieve the perfect combination of accuracy and speed. The power supply voltage range is 5 V to 24 V. The amplifier has a patented rail transmission level, which can drive 0.5 volt power, and at the same time, the source or sinks up to 30 mAh. There is also a negative power supply mode from a level 3 power supply from a positive power supply to the negative power supply. It is possible to exceed JFET input range, because the auxiliary bipolar input level works with the input voltage until the power supply. The way of working in the amplifier is like they have a rail -to -track input, and there is no phase reversal behavior of the co -mode voltage in the power supply.

AD8065/AD8066 has 7 nv/√Hz voltage noise and 1 MHz 2 V P-P signal 88 DBC distortion, which is an ideal choice for high-resolution data collection system. Their low noise, the Asian PA input current, accurate offset, and high speed make them an excellent front amplifier for the application of the fast photoelectric diode. The speed and output driving capacity of AD8065/AD8066 also make them very useful in video applications.

The closed -loop frequency response AD8065/AD8066 is a typical voltage feedback amplifier, and its opening frequency response can be approximately similar to the integral device response shown in Figure 53. Basic closed frequency response of inverter and non -inverted configuration can be obtained from the diagram shown. Non -reversible closed ring frequency response The solution of the transmission function

Among them

closed loop 3 db frequency

Reverse closed ring frequency response

123]

closed loop 3 db frequency

The noise gain to the inverse ratio (RF+RG)/RG. This simple model is precise for noise gain than 2. Due to the effect of other polar points in the frequency response of the actual computing amplifier, the actual bandwidth of the noise gain at 2 or less will be higher than the bandwidth predicted by this model.

FIG. 54 shows the DC error of the voltage feedback amplifier. Non-reversal configuration

If RS u003d RF | | | RG, the voltage error caused by IB+and IB-is the least (although the input current of AD8065 exceeds 20Pa than 20Pa This may not be a problem). In order to include the co -mode and power suppression effect, the total VO can be modeled as:

Vosnom is the offset voltage specified under the nominal conditions. Compared with the changes in nominal conditions, PSR is a power suppression, u0026#8710; VCM is a change in the co -mode voltage relative to the nominal conditions, and CMR is co -mode inhibition.

Broadband operation

Figure 42 to 44 shows a broadband characteristic circuit for gain to+1,+2, and -1. The source impedance at the harmony knot (RF | | RG) will form a pole in the ring response of the amplifier, and the input capacitor of the amplifier is 6.6 PF. If the time constant formed is too low, it may cause peak and ringing. It is recommended to use the feedback resistor of 300 to 1 k because they will not over -reduce the load of the amplifier, and the time constant formed will not be too low. The peak value in the frequency response can be compensated by small capacitors (CF) with feedback resistors, as shown in Figure 12. This shows the impact of different feedback capacitors on the peak and bandwidth of non -Easy G u003d+2 amplifier.

In order to obtain the best stability and best distortion, the impedance of the AD8065/AD8066 input terminal should be matched. This will minimize the effects of non -linear co -modular capacitance that reduces communication performance.

Actual distortion performance depends on many variables:

u0026#8226; Closed -loop gain

u0026#8226; 123] u0026#8226; amplifier load

u0026#8226; signal frequency and amplitude

u0026#8226; circuit board layout

Please refer to Figure 16 to 20. The AD8065 used in the low -gain inverter application will obtain the lowest distortion because this eliminates the co -mode effect. Higher closed -loop gain can lead to worse distortion performance.

Input protection

Input of AD8065/AD8066 Back protection-back polar diode between the input terminals and the ESD diode of the power supply. This allows the input level to have Pipan's input current, which can withstand the electrostatic discharge event (human model) with up to 1500 volts without degeneration.

Excessive power consumption of protecting the device will destroy or reduce the performance of the amplifier. Different voltages greater than 0.7 V will generate approximately (| v+ v 0.7 v)/RI input current, where RI is the resistance to the input series. For the input voltage beyond the positive power supply, the input current is about (VI VCC 0.7)/RI. Except for negative power, the input current is about (VI Vee+0.7)/RI. If the input of the amplifier is to be input more than 0.7V or the input voltage other than the amplifier power supply, the input current should be limited to 30mA by the input resistor (RI) of the appropriate size, as shown in Figure 55.

Thermal factors

Under the 24 volt power and 6.5 mm quiet current, AD8065 consumes 156 mcwils without load. The power consumption of AD8066 is 312 MW. This can lead to obvious thermal effects, especially in small SOT-23-5 (thermal resistance of 160 ° C/W). VOS temperature drift is adjusted to ensure the maximum drift of 17 μV/° C. Therefore, because the preheating effect of AD8065/AD8066 in SOT-23-5 packaging can reach 0.425 MV at 24 V.

The temperature increases by 1.7 times every 10 ° C. Compared with a single 5V power supply, the IB value of the 24 V power supply will be nearly 5 times higher.

The heavy load will increase power consumption and increase the chip knot temperature, as described as the maximum power consumption part. Be careful not to exceed the rated power consumption of packaging.

Input and output overload behavior

AD8065/AD8066 has internal circuits to prevent phase reversal caused by the driver input level. The simplified schematic diagram of the input level includes input protection diode and anti -phase circuit, as shown in Figure 56.

When the input co -mode voltage exceeds a certain threshold, the bias current of the input of the JFET pair will be closed, and the bias current of the auxiliary NPN pair will be connected to take over the control of the amplifier.When the input co -modular voltage is restored to a feasible working value, the FET level is re -connected, the NPN class is turned off, and normal work is restored.

The NPN is maintained in the case of the input voltage to reach the positive power supply, so this is a pseudo -rail input level. For operations that exceed the FET -level co -mode limit, the V of the amplifier will be changed to the offset of the NPN pair (the average value is 160 μV, the standard deviation is 820 μV), and the I will increase to the base current of the NPN pair to 45 μA (see the picture in the figure 32). The operating system B switching or recovery time is about 100ns, see Figure 27.

The output transistor of the rail -to -orbit output level has a circuit to limit the saturation level when the output is over -driven. This helps output recovery time. Figure 24 shows the output recovery of the 0.5 V output on the ± 5 V power supply.

Layout, grounding, and bypass precautions

Power sources

The power pipe foot is actually an input terminal. Be careful to apply a DC voltage with no noise and stable. The purpose of the bypass container is to generate low impedance from the power to the ground at all frequencies, thereby diversion or filtering most of the noise.

The design of the decoupling scheme is to minimize bypass impedance at all frequencies and parallel combination capacitors. 0.1 μF (X7R or NPO) chip capacitor is very important, and should be closer to the amplifier packaging as much as possible. In most cases, at high frequencies, each capacitor only needs one 4 钽 钽.

ground

In the densely encapsulated PC board, the floor layer is very important for the decentralized current to minimize the parasitic inductance. However, understanding the flow of current in the circuit is essential to achieve effective high -speed circuit design. The length of the current path is proportional to the size of the parasitic inductance, so it is proportional to the high frequency impedance of the path. Sensing high -speed currents in the grounding circuit generate unnecessary voltage noise.

The length of the high -frequency side electric container lead is the most critical. Parasitic inductance in bypass ground will play a role in the low impedance of bypass capacitors. Place the ground wire of the bypass container in the same physical location. Since the load current also comes from the power supply, the grounding of the load impedance shall be in the same physical location as the bypass capacitor. For a larger value capacitor at a lower frequency, the distance between the current return path is not so important.

Leakage current

Poor PC plate layout, pollutant and circuit board insulator material will produce leakage currents that are much larger than AD8065/AD8066 input bias current. Any voltage difference between the input terminal and the nearby operation will generate a leakage current through the PC board insulation, for example, 1 V/100 G u003d 10 PA. Similarly, any pollutants on the circuit board will cause serious leakage (skin oil is a common problem). For significantReduce leakage, add a protective ring (shielding) around the input and input terminal, and the input terminal and the input terminal have the same voltage potential. In this way, there is no voltage potential between the input terminal and the surrounding area to set up any leakage current. In order to make the protective ring fully effective, it must be driven by a relatively low impedance power supply, and it should be completely surrounded by a multi -layer board to completely surround all aspects of the input lead, above and below.

Another effect that may cause leakage current is the charge absorption of the insulator material itself. Try to reduce the amount of materials between the input wires and the protective ring will help reduce absorption. In addition, in some cases, low absorption materials, such as Teflon u0026#174; or ceramics.

Input capacitance

With the bypass and grounding, the high -speed amplifier can be sensitive to the input and ground between parasitic capacitors. A small amount of capacitors will reduce the input impedance during high frequency, thereby increasing the gain of the amplifier, causing the frequency response to peak or even oscillation, if severe. It is recommended to place the external passive element connected to the input pin at the position of the input as close to the input to avoid parasitic capacitors. The ground and power plane must keep a small distance from the input pins of all the circuit board.

Output capacitance

To a small degree, the parasitic capacitance on the output will cause the peak and bell at the frequency response. There are two ways to minimize their influence.

u0026#8226; as shown in Figure 57, a small value resistor (RS) is connected with the output to isolate the output level of the load capacitor from the amplifier. A good choice value is 20 (see Figure 10).

u0026#8226; increased the phase margin through higher noise gain, or add an electrode with a parallel resistor and a capacitor at the output end.

Input and output coupling

In order to minimize the capacitor coupling between input and output, the output signal trajectory should not be parallel to the input.

Broadband photoelectric diode front placed large device

FIG. 58 shows an I/V converter with photoelectric diode electrical models. The basic transmission function is:

Among them, the iPhoto is the output current of the photoelectric diode, and the parallel combination of RF and CF sets the signal bandwidth.

The stable bandwidth that can be obtained by using the front amplifier is radio frequency, the amplifier gain bandwidth multiplication, and the total capacitance (including CS and the amplifier input capacitor). RF and total capacitors generate a pole in the loop transmission of the amplifier, which may lead to peak and instability. Increasing CF will produce 0 in the environment, which compensates the effect of the extreme point and reduces the signal bandwidth. It can be seen that the signal bandwidth of the 45 ° phase margin (f (45)) is expressedFormat

Among them, the FCR is the cross frequency of the amplifier, RF is a feedback resistor, and CS is the total capacitance of the amplifier to seek and settle (amplifier+photoelectric diode+plate parasitic).

The CF value generated by f (45) can be displayed as:

In this case, the frequency response will display the peak and 15 of about 2 dB and 15 %Of the super -adjustment. The instantaneous bandwidth reduction of half of the CF will cause half of the frequency response to slowly.

The output noise of the front placement exceeds the frequency as shown in Figure 59.

The pole transmission in the ring circuit is transformed into 0 in the noise gain of the amplifier, which leads to the enlarged frequency of the input voltage noise. The ring transmission 0 introduced by CF limits the magnification. The noise gain bandwidth expansion exceeds the bandwidth of the front amplifier signal, and eventually decreased by the loop gain of the amplifier. It is recommended to keep the input -end impedance matching to eliminate the peak effect of the co -modular noise, which will increase the output noise.

The output voltage noise spectrum density is marked with the frequency of frequency, and then take the square root to get the total effective validity value of the output noise of the front amplifier. Table 5 summarizes the approximate value of the amplifier, feedback resistance and source resistance. It also lists the noise component of RF u003d 50K , CS u003d 15pf and CF u003d 2pf (about 1.6MHz).

High -speed JFET input instrument amplifier

Figure 60 shows a high input impedance using AD8065/AD8066 Example of high -speed meter amplifier. The passing function of the DC is:

For G u003d+1, it is recommended to set the feedback resistance resistance of the two front places to the low value (for example, 50 source impedance is to be 50 ). G u003d+1 bandwidth is 50 mHz. In order to obtain a higher gain, the bandwidth will be set up by the front placed, which is equivalent to

The co -mode suppression of InAMP is mainly determined by the matching of resistance ratio R1: R2 to R3: R4 to determine Essence It can be estimated that

The total resistance of the front amplifier is equal to Torf | | 0.5 (RG). This is the value used to match the purpose.

Video buffer

In the video output of AD8061, it makes it a useful video buffer, as shown in Figure 61.

g u003d+2 configuration compensation signal due to voltage separation due to signal terminal. For a signal of up to 7MHz, the bufferKeep a flat degree of 0.1DB from low amplitude to 2V P-P (Figure 7).Under the power conditions of ± 5 V, the differential gain and phase measurement values are 0.02%and 0.028 °, respectively.

The size of the shape