The CDCE949 and CDCEL949 are low-cost, high-performance, programmable clock synthesizers, multipliers and dividers based on modular PLLs. They generate up to 9 output clock frequencies from a single input. Each output is in-system programmable for up to four independently configurable PLLs for any clock frequency up to 230 MHz. CDCEx949 has independent output power pins, VDDOUT, 1.8 V for CDCEL949, 2.5 V to 3.3 V. For CDCE949. Input accepts external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is suitable for most applications. The value of this load capacitance is programmable from 0 to 20 pF. Additionally, an on-chip VCXO can be selected, allowing the output frequency to be synchronized to an external control signal, a PWM signal.

feature

1 member of the programmable clock generator

family

- CDCEx913: 1 PLL, 3 outputs

- CDCEx925: 2 PLLs, 5 outputs

- CDCEx937: 3 PLLs, 7 outputs

- CDCEx949: 4 PLLs, 9 outputs

In-System Programmability and EEPROM

- Serial programmable volatile registers

- Store customer's non-volatile EEPROM

set up

Flexible input clock concept

- External crystal: 8 to 32 MHz

- On-chip VCXO: pull range ± 150 ppm

- Single-ended LVCMOS, up to 160 MHz

Selectable output frequency up to 230 MHz

Low noise PLL core

- PLL loop filter component integration

- Low period jitter (60 ps typical)

Separate output power pins

- CDCE949: 3.3 V and 2.5 V.

- CDCEL949: 1.8 V

Flexible clock driver

- Three user definable control inputs

[S0/S1/S2], e.g. SSC selection,

Frequency switching, output enable or power down

- Generate high precision clock for video,

Audio, USB, IEEE1394 , RFID, Bluetooth™, WLAN, Ethernet™ and GPS - generated using common clock frequencies using TI-DaVinci™, OMAP™, DSP

- Programmable SSC modulation

- Enable 0-PPM clock generation

1.8V device core power supply

Wide temperature range: -40°C to 85°C

Available in TSSOP package

Development and programming kit design and programming for Easy PLL (TI Pro-Clock?)

2 apply

D-TV, STB, IP-STB, DVD player, DVD recorder and printer

Typical Application Schematic

Deep M/N divider ratio allows to generate zero ppm audio or video, network (WLAN, BlueTooth™, Ethernet, GPS) or interface (USB, IEEE1394, Memory Stick) clocked from a reference input frequency, e.g. 27 MHz. All PLLs support SSC (Spread Spectrum Clocking). SSC can be a center-propagating or down-propagating clock. This is a common technique for reducing electromagnetic interference (EMI). Based on the PLL frequency and divider settings, the internal loop filter components automatically adjust to achieve high stability and optimize the jitter transfer characteristics of each PLL. The device supports non-volatile EEPROM programming, making it easy to customize the device to the application. It is preset to the factory default configuration. It can be reprogrammed for different application configurations prior to PCB assembly, or by in-system programming. All device settings are programmable via the SDA and SCL buses, a 2-wire serial interface. Three programmable control inputs S0, S1 and S2 can be used to control various aspects of operation, including frequency selection, changing SSC parameters to reduce EMI, PLL bypass, power down and selection of either LOW or 3 states for the output disable function between. The CDCEx949 can operate in a 1.8 V environment. Its operating temperature range is -40°C to 85°C.

6-pin configuration and function

Parameter measurement information

Test load diagram

Test load for 50Ω board environment

The CDCE949 and CDCEL949 devices feature a modular PLL, low cost, high performance, programmable clock synthesizer, multiplier and divider. They generate up to 9 output clock frequencies from a single input. Each output can be programmed in-system for any clock frequency up to 230 MHz, using one of the

Four integrated configurable PLLs. CDCEx949 has independent output power supply pin VDDOUT, CDCEL949 is 1.8 V, 2.5 V to 3.3 V is CDCE949. Input accepts external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is suitable for most applications. The value of the load capacitance is programmable from 0 to 20 pF. In addition, an optional on-chip VCXO allows the output frequency to be synchronized to an external control signal, a PWM signal. Deep M/N divider ratio allows generation of 0 ppm audio and video, network (WLAN, Bluetooth, Ethernet, GPS) or interface (USB, IEEE1394, memory stick) clocked from a reference input frequency, e.g. 27 MHz. All PLLs support Spread Spectrum Clocking (SSC). The SSC can be a center-spread or a spread-out clock. This is a common technique for reducing electromagnetic interference (EMI). Based on the PLL frequency and divider settings, the internal loop filter components automatically adjust to achieve high stability and optimize the jitter transfer characteristics of each PLL. The device supports non-volatile EEPROM programming, making it easy to customize the device to the application. It is preset to the factory default configuration (see Default Device Settings). It can be reprogrammed to a different application configuration prior to PCB assembly, or through in-system programming. All device settings are programmable via the SDA and SCL bus, which is a 2-wire serial interface. Three programmable control inputs S0, S1 and S2 can be used to control various aspects of operation, including frequency selection, changing SSC parameters to reduce EMI, PLL bypass, power down and selection of either LOW or 3 states for the output disable function between. The CDCEx949 can operate in a 1.8 V environment. Its operating temperature range is -40°C to 85°C.

Functional block diagram

The S1/SDA and S2/SCL pins of the CDCEx949 are dual function pins. In default configuration they are defined SDA/SCL for serial interface. They can be programmed as control pins (S1/S2) EEPROM by setting the relevant bits. Note that changes to the control register (bit[6] of byte[02]) have no effect before they are written to the EEPROM.

After setting them as control pins, the serial programming interface is no longer available. However, if VDDOUT is forced to ground, the two control pins S1 and S2 are temporarily used as serial programming pins (SDA/SCL). S0 is not a multipurpose pin, just a control pin. The internal EEPROM of the CDCEx949 is pre-configured as shown in Figure 6 (the input frequency is passed through the output as the default value). This allows the device to operate in default mode without additional steps of production programming. Default settings are displayed when powered on or off or powered on

sequence until the user reprograms it to a different application configuration. A new register setting is programmed via the serial SDA/SCL interface.

Default device settings diagram

The CDCEx949 operates as a slave device on a 2-wire serial SDA/SCL bus, compatible with the popular SMBus or I2C bus specifications. It operates in standard mode transfers (up to 100 kbps) and fast mode transfers (up to 400 kbps) and supports 7-bit addressing. The S1/SDA and S2/SCL pins of the CDCEx949 are dual function pins. Use them in the default configuration as the SDA/SCL serial programming interface. They can be reprogrammed as general purpose control pins, S1 and S2, by changing the corresponding EEPROM settings, Byte 02, Bit.

Timing Diagram for SDA/SCL Serial Control Interface