General Instructions
The W83627HF and W83627F are products of Winbond's most popular I/O series. They offer a brand new interface, the LPC (Low Pin Count) interface, which will be available in the next generation of Intel chipsets. This interface, as the name suggests, is intended to provide an economical I/O interface implementation with a lower pin count and still maintain the same performance as its ISA interface counterpart. Compared to ISA, about 40 pin counts are kept in LPC I/O.
implement. With this extra freedom, we can implement more devices on a single chip. The integration of a game port and a MIDI port is demonstrated in the W83627F/HF. It is completely transparent in that it does not require any BIOS or device driver updates other than chip-specific configuration. The W83627F/HF's disk drive adapter functions include compatibility with the industry standard 82077/765 , data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, interrupts and DMA logic. The extensive functionality integrated on the W83627F/HF greatly reduces interfacing with floppy disk drives. The W83627F/HF supports four 360K, 720K, 1.2m, 1.44m or 2.88m disk drives and data transfer rates of 250 kb/s, 300 kb/s, 500 kb/s, 1 MB/s and 2 MB/s.
The W83627F/HF provides two high-speed serial communication ports (UART), one of which supports serial infrared communication. Each UART includes a 16-byte transmit/receive FIFO, a programmable baud rate generator, full modem control capabilities and a processor interrupt system. Two UARTs provide baud rates up to 115.2k bps for legacy speeds, and baud rates for premium speeds.
Supports 230K, 460K or 921K bps for high-speed modems. In addition, W83627F/HF provides infrared functions: IRDA 1.0 (SIR is 1.152K bps) and TV remote control infrared (user infrared, supports NEC, RC-5, extended RC-5 and RECS-80 protocols).
The W83627F/HF supports a PC-compatible printer port (SPP), a bidirectional printer port (BPP) and, in addition, an enhanced parallel port (EPP) and an extended capability port (ECP). Also available via the printer port interface pins: Extended FDD Mode and Extended 2FDD Mode, allowing one or two external floppy drives to be connected.
Configuration registers support mode selection, function enable/disable, and power-down functions.
choose. In addition, the configurable PNP function is plug-and-play compatible.
The demands of Windows 95/98TM have made system resource allocation more efficient than ever.
The W83627F/HF provides an ACPI (Advanced Configuration and Power) compliant function interface), including support for legacy and ACPI power management via the PME or PSOUT# function pins. For OnNow keyboard wakeup, OnNow mouse wakeup, OnNow CIR wakeup.
The W83627F/HF also features automatic power management to reduce power consumption.
The keyboard controller is based on an 8042 compatible instruction set and a 2K byte programmable read-only memory. and a 256-byte RAM bank. Keyboard BIOS firmware can be used with optional amikeytm multikey/42TM or customer code. W83627F/HF through a set of general purpose I/O ports. These GPIO ports can be used as simple I/O or can be configured individually. Provides a predefined fallback function. General purpose port 1 is designed to operate even in power down mode (VCC off).

The W83627F/HF is fully compliant with Microsoft PC98 and PC99 hardware design guidelines. In addition, W83627F/HF meets PC98/PC99 power requirements. Management: ACPI and DPM (Device Power Management).
The W83627F/HF includes a game port and a MIDI port. The game port is designed to support 2 joysticks and can be used with all standard PC game control devices, they are for entertainment or consumer computers.
Only W83627HF supports PC hardware status monitoring. It can be used to monitor several key hardware parameters of the system, including power supply voltage, fan speed and temperature, which are very important for the stable operation of high-end computer systems, correctly. Features Overview Compliant with LPC specification 1.0 Support ldrq (lpc dma), serirq (serial IRQ) including Winbond I/O All functions of W83977TF and W83977EF Integrated hardware monitoring function Compliant with Microsoft PC98/PC99 Hardware Design Guidelines Support DPM (Device Power Management), ACPI Programmable Configuration Settings Single 24 or 48 MHz Clock Input IBM PC Compatible Disk Drive System Variable Write Precompensation with Track Select Capability All overspeed and underload conditions Built-in address mark detection circuitry simplifies reading electronics FDD antivirus with software write protection and FDD write enable signal (write data signal forced to disable) Supports up to four 3.5" or 5.25" The floppy disk drive fully complies with the industry standard 82077360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2Mbps data transfer rate supports 3-mode FDD and its Win95/98 driver Two high-speed 16550 compatible UARTs, 16-byte transmit/receive FIFO compatible with MIDI Fully programmable serial interface Features: --- 5, 6, 7 or 8 characters --- Even, odd or no parity bit generation/detection --- 1, 1.5 or 2 Stop Bit Generation Internal Diagnostic Capabilities: - Loop Control for Communication Link Fault Isolation - Interrupt, Parity, Overflow, Frame Error Analog 1 to (216 Maximum baud rate: 14.769 MHz is 921K bps, 24 MHz is 1.5M bps. Infrared supports IRDA version 1.0 SIR protocol, the maximum baud rate is up to 115.2kbps Support Sharp ASK-IR protocol, the maximum baud rate is up to 57600 bps Support Consumer Infrared Parallel Port Compatible with IBM Parallel Port Support PS/2 Compatible Bi-directional Parallel Port Support Enhanced Parallel Port (EPP), IEEE 1284 Specification Disk drive B supported; Extended 2FDD mode supports disk drives A and B. Enhanced printer port via parallel port Rear drive current protection Keyboard controller £8042, optional F/Wphoenix Multikey/42TM according to AmikkeyTM or customer code with 2K bytes of programmable read-only memory and 256 bytes of RAM Asynchronous access to two data registers and one status register Software compatibility with 8042 support for PS/2 mouse support for port 92 support for interrupt and polling mode fast gate A20 and hardware keyboard reset 8-bit timer/counter supports binary and BCD algorithm 6 MHz , 8 MHz, 12 MHz or 16 MHz operating frequency

Game port supports two independent joysticks supports two axes (X, Y) and two buttons (A, B) for each joystick Controller MIDI interface baud rate is 31.25kbaud.
16-byte output FIFO general purpose I/O ports 22 programmable general purpose I/O ports General purpose I/O ports can be used as simple I/O ports, interrupt steering input, watchdog timer. output, power LED output, IR I/O pin, KBC control I/O pin, floating LED output, RSMRST# signal, PWROK signal, buzzer output works in power-down mode (GP1 only) OnNow function can be Wake up keyboard via programmable key Wake up mouse via programmable key CIR wake up from all ACPI sleep states (S1-S5) Hardware monitor function (W83627HF only) 5 VID input pins for CPU V Core recognition 3 thermal inputs from optional remote thermistor or 2n3904 transistor or PentiumTM II (descaling) thermal diode output 7 positive voltage inputs (typically +12V, -12V, +5V, -5V, +3.3V , VCOREA, VCOREB) 2 intrinsic voltage monitoring (vbat typical, +5vsb) fan speed monitoring input fan speed control built-in open circuit detection circuit Programmable hysteresis and setting of all monitoring items High temperature indicates output automatic power-on voltage detection buzzer Release SMI, IRQ, OVT to activate system protection Compatible with Intel LDCMTM/Acer ADMTM

LPC (Low Pin Count) Interface
The LPC interface replaces being the host (chipset) and peripheral (Winbond I/O). Data transfers on the LPC bus are serialized over a 4-bit bus. The general features of the interface implemented in Winbond LPC I/O are: • A control line, LFRAME, that the host uses to start or stop the transfer. No peripheral device drives this signal.
LAD[3:0] bus, used for serial communication information. The information passed is the type of loop, loop direction, chip select, address, data, and wait states.
The mr (master reset) of the Winbond ISA I/O is replaced with a low reset signal, i.e. lreset, inWinbond LPC input/output.
Winbond LPC I/O requires an additional 33 MHz PCI clock for synchronization.
DMA requests are issued through LDRQ.
Interrupt requests are issued through serirq.
Power management events are published through PME. Compared to its ISA counterpart, the LPC implementation can save up to 40 pin counts for free (see table below). Integrate more devices on one chip. The conversion from ISA to LPC is software transparent, which means there is no BIOS or device drivers. Updates are required, except for chip-specific configurations.

The fdc function describes the w83627hf of the floppy disk controller integrates all the required logic control with the floppy disk. The fdc implements a PC/AT or PS/2 solution. Fully compatible values for the default values of programmable options. The First In First Out (FIFO) provides better system performance in multi-master systems. 2 mbit/s data rate on the stand of the digital data splitter. The fdc includes the following blocks: AT interface, precompensation, data rate selection, digital data splitter, first in first out (FIFO), and fdc core. AT interface This interface is controlled by standard asynchronous signals: #RD, WR #A0, A3, IRQ, DMA, and a data bus. The address select lines in the configuration register, first in first out (FIFO) and control/status registers. This interface can switch between PC/AT model, 30, or PS/2 normal mode. The PS/2 registry is a superset of a set of registry on one side of the PC/AT. FIFO (data) in first in first out (FIFO) is 16 bytes in size and the GLT programmable read-only threshold. All command line parameter information and data transfers to the board through the FIFO. The gov data is transferred by rqm and god in the master status register.
The FIFO mode defaults to disabled reset in any form. This maintains PC/AT five compatibility. The default value can be changed via the configure command. The advantage of the FIFO principle is that it allows the latency of DMA in a large system not to fail due to disk errors. The following table uses first-in-first-out (FIFO) for delays for several examples. The data is based on the following formula:

At the start of the command, the FIFO is always disabled and the command parameters must be set based on the RQM and DIO bits in the main status register. When the FDC enters a command to execute the stage, it clears the FIFO of any data to ensure that invalid data is not transmitted. Overflow and underrun will terminate the current command and data transfer. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. A read requires the host to delete the remaining data in order to enter the results stage. A DMA transfer is enabled using the specified command and is activated by the FDC via the DRQ pin during the data transfer command. By asserting the dack and the address are not necessarily valid.
Note that if the DMA controller is programmed to operate in verify mode, the dummy read is performed by the FDC based on DACK only. Only if the FDC is configured in byte mode (FIFO disabled) and programmed to read. Use the new verify command to perform the operation after enabling FIFO. DMA operations are not required.
The function of the data separator is to lock the incoming serial read data. When locked, the serial front end of the chip is logically provided with a clock synchronized with the read data. This synchronous clock (called the data window) is used to sample the bit cells and alternate states of the clock portion. Serial-to-parallel conversion logic separates the read data into the clock and data bytes. The Digital Data Separator (DDS) consists of three parts: control logic, error adjustment and speed tracking. The DDS circuit ideally cycles every 12 clock cycles. Any data pulse input will be synchronized and then adjusted by instant error adjustment. The control logic will be input for each pulse. In any loop without data pulses, the DDS loop is velocity based. A digital integrator is used to track velocity changes in the incoming data stream.
Write precompensation logic is used to minimize bit shifts in the RDData stream from disk. drive. Bit shifting is a known phenomenon in magnetic media that relies on disk media. There are also floppy drives. The FDC monitors the bit stream sent to the driver. The required data pattern precompensation is well known. Depending on the mode, the bits are moved either earlier or later. relative to the surrounding bits.
The vertical recording mode FDC can also be connected directly to a vertical recording floppy disk drive. Perpendicular recording differs from traditional longitudinal methods because the magnetic bits are oriented vertically. This scheme packs more data bits into the same area.
FDCs with perpendicular recording drives can read standard 3.5-inch floppy disks and can read and write perpendicular media. Some manufacturers offer drives that can read and write vertical media in both standard and vertical media drives.

Usually it is. Vertical mode requires a data rate of 1 Mbps for the FDC. At this data rate FIFO relieves host interface bottlenecks because data transfers are fast to or from disk.
The FDC core W83627HF FDC is capable of executing 20 commands. Each command is initiated by a multibyte transfer from the microprocessor. The result can also be a multibyte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result. Commands the microprocessor to send the controller all the information it needs to perform a specific action. The execution controller performs the specified action. After the resulting operation is complete, status information and other housekeeping information is provided to the microprocessor.

ACPI register function
The W83627HF supports ACPI and legacy power management. The switch logic management block of the power supply generates an SMI interrupt in legacy mode and a PME interrupt in ACPI.
model. New ACPI functionality to route SMI/PMELogic output to SMI or TOPME.
The smi/pm logic routes to smi only when pme_en=0 and smipme_oe=1. Similarly,
SMI/PME can route to PME only when PME_en=1 and SMIPME_oe=1.