The BQ29330 is a 2-series, 3-series and 4-series Li-Ion battery pack fully protected analog front end (AFE) IC with built-in 2.5 V, 16 mA and 3.3 V, 25 mA low dropout voltage regulators (LDO). The bq29330 also integrates an IC-compatible interface to extract battery parameters such as battery voltage, individual battery voltage and control output status. Other parameters such as current protection thresholds and delays can also be programmed into the bq29330 to increase the flexibility of the battery management system.

1 Features

2 series, 3 series or 4 series battery protection NMOS FET driver for charging and discharging

control FET

Can interface directly with bq803x-based host control Can initiate sleep and ship power Gas Gauge home mode host Watchdog and POR Integrated 2.5V, 16mA LDO

Provides single battery voltage and battery integrated 3.3V, 25mA LDO

The battery management host voltage supply voltage range is 4.5 V to 28 V.

Capable of Sensing Operation at 5mΩ Low Supply Current 100µA Typical

Resistor Integrated Cell Balance Driver

A generation

2C compliant user interface allows access to application battery information laptop

Programmable Thresholds and Delays Medical and Test Equipment Discharge Overload Shorts and Shorts

The instrumentation and measurement system circuits are responsible for

System diagram

The bq29330 provides safety protection conditions for overload, charge short circuit and discharge short circuit. It can also provide battery overvoltage, battery overvoltage and battery undervoltage protection to the battery management host. The bq29330 automatically shuts down the FET driver according to internal configuration settings during overload, short-circuit on charge, and short-circuit on discharge conditions. This communication interface allows the host to observe and control the status of the bq29330, enabling the unit

Balance, enter different power modes, set current protection level, and set blanking delay time. Cell balancing for each cell can be done via the cell bypass path integrated in the bq29330, or it can be enabled via an internal control register with an I-accessible 2C-compatible interface. The maximum bypass current is set by an external series resistor and internal FET on-resistance ( 400 Ω typical).

Calorie Information

bq29330 heat meter (1) TSSOP (DBT) QFN (RSM) unit 30 PIN codes 32 PIN codes

JA, High-K Junction to Ambient Thermal Resistance 81.4 37.4

JC (top) junction to case (top) thermal resistance 16.2 30.6

JB Junction-to-Board Thermal Resistance 34.1 7.7°C/W

JT Junction Top to Characterization Parameters 0.4 0.4

JB Junction to Board Characteristics 33.6 7.5

JC (bottom) junction to case (bottom) thermal resistance N/A 2.6

Package Option Pin Diagram

TSSOP packaging (top view)

RSM Package (Top View)

Password function

The CELL-1 28 outputs the calibrated value of the measured battery voltage.

CELL + 2 29 outputs the calibrated value of the measured battery voltage.

REG 3 30 Integrated 2.5V Regulator Output

VSS 4,23 31,21 Power Ground

XRST 5 32 Active low output

SRN 6 1 current detection terminal

Current sense positive terminal when charging with respect to SRN; current sense negative terminal when SRP 7 3 is discharging with respect to SRN

VC5 8 4 Induced voltage input terminal for most negative cells; balanced current input for at least positive cells.

Induced voltage input terminal for min positive cell, balance current input for min positive cell and return to VC4 9 5

Balance the current of the third most positive cell.

Induced voltage input terminal of the third largest positive battery, balance current input of the third largest positive battery, VC3 10 6

and returns the balancing current of the second largest positive cell.

The induced voltage input terminal is the second largest positive battery, and the balance current input is the second largest VC2 11 7

Positive cells, the return equilibrium current of most positive cells.

Induced voltage input terminals for most positive cells, balance current input for most positive cells, and VC1 12 8

Battery pack measurement input

BAT 13 9 Device power input

CHG 14 11 charge pump to charge N-CH FET gate drive

DSG 16 13 Charge Pump Output, Discharge N-CH FET Gate Drive

PACK 17 15 PACK positive terminal and backup power

VCC 19 16 Supply voltage

ZVCHG 20 17 connect the pre-charged P-CH FET driver here

GPOD 21 18 NCH FET open drain output

PMS 22 19 Determine CHG output status on POR

LEDOUT 24 22 3.3-V output for LED display power

TOUT 25 23 provides thermistor bias current

Functional block diagram

Security State Diagram

Function Description

Low Voltage Output Regulator (LEDOUT) The input to this regulator can come from the VCC or BAT terminals. The output is a fixed voltage with a typical value of 3.3 V, the output capacitance is the smallest, the stable operating current is 2.2 μF, and the internal current is also very small and limited. This output is used for LED drive, REG (2.5 V), and power supply for the bq29330's internal circuitry. During normal operation, the regulator limits the output current to typically 50 mA. The DSG and CHG FET drivers are low (FET = OFF) until the internal voltage regulator circuit is properly powered. Low Voltage Output Regulator (REG) The input to this regulator can be from an LED (3.3 V). The output is typically 2.5 V, min

The output capacitor is stable to 1µF and is internally current limited. During normal operation, the regulator limits the output current to 50 mA. Initialization From the shutdown point of view, the bq29330 requires a voltage PACK pin that is greater than the start-up voltage (VSTARTUP) to integrate the voltage regulator and provide the voltage regulator power supply. Once the REG output is stable, the power supply to the regulator is switched to VCC. After the regulator starts, it continues to run through the VCC input. If the VCC input is below the minimum operating range, the bq29330 will not operate if the PACK input supply is removed. If the voltage of VLED falls below about 2.3 V, the internal circuit will turn off the FET and disable all controllable voltage functions including REG, LEDOUT and TOUT outputs. The CHG and DSG FETs are initially driven low (OFF) and the ZVCHG FETs are driven low (ON). Overload detection Overload detection is used to detect abnormal current in the discharge direction. This feature is used to protect the pass FET, cell and any other inline components from overdischarge current conditions. The detection circuit also includes a blanking delay before driving the control of the pass FET to the OFF state. The overload detection voltage is set in the OLV register, and the delay time is set in the OLD register. The thresholds can be individually set from 50 mV to 205 mV in 5 mV steps, with a default of 50 mV. If the RSNS bit in the FUNCTION_CTL register is set to 1, the voltage threshold, programmable step size, and hysteresis are divided by 2. Short circuit for charge and short circuit in discharge detection The charge short circuit current and discharge detection short circuit are used to detect severely abnormal charges in the direction of charge and discharge, respectively. This safety feature is used to protect the pass FET, battery and any other inline components during overcurrent conditions. The detection circuit also includes a blanking delay before driving the control of the pass FET to the OFF state. charging short circuit

The threshold and delay time are set in the SCC register. The discharge threshold and delay time short circuit are set in the SCD register. The short-circuit threshold is programmable from 100 mV to 475 mV in 25 mV steps. If the RSNS bit in the FUNCTION_CTL register is set to 1, the voltage threshold, programmable step size, and hysteresis are divided by 2. Overload, short-circuit charge and short circuit with delay in unloading

Overload delay (default = 1 ms) allows the system to temporarily accept a high current state without disconnecting power from the load. The delay time can be increased by the OLD register, programmable from 1 ms to 31 ms in 2 ms steps. Charge shorts and shorts in discharge delay (default=0µs) can be programmed in the SCC and SCD registers. These registers can be programmed from 0 μs to 915 μs in 61 μs steps.

Latch Clear (LTCLR)

In the event of a protection fault, the state is locked. To clear the fault flag, toggle (from 0, set 1, then reset to 0)

LTCLR bit (bit 7) in the STATE_CONTROL register. The OL, SCC, SCD and WDF bits thus unlock functionality. The FET can now be controlled by programming the OUTPUT_CONTROL register and XALERT to clear the output by reading the STATUS register.

LTCLR and XLAERT clear timing

POR and Watchdog Reset (XRST)

Activate the XRST pin by activating the REG output. This keeps the master constant during reset for tRST periods, allowing VREG to stabilize before the master is released from reset. When the regulator supply is down, XRST is valid below 1.8 V of the regulator voltage. In addition, when a watchdog failure is detected, XRST is also activated to ensure a valid reset of the battery management host.

XRST Timing Diagram - Power-Up and Power-Down

Watchdog Input (WDI)

In determining fault detection, the WDI input needs to be used as the time base for delayed timing and as part of the use of the system watchdog. Initially, the watchdog monitors the primary oscillator startup; if the host does not respond within tWDINT tRST expires, then the bq29330 shuts down CHG, DSG and ZVCHG FETs. It then activates an XRST output to attempt to reset the host. After the watchdog is started during wakeup, it monitors the host for an oscillation stop condition, defined as the period of tWDWT where no clock input is received. If the oscillator stop condition is asserted, the watchdog turns off the CHG, DSG and ZVCHG FETs. The bq29330 then activates the XRST output to attempt to reset the host. If master clock oscillation is started after reset, the bq29330 still sets the WDF flag until it is cleared. See the LTCLR section for more details on clearing the fault flag. In sleep mode, the watchdog function is not disabled.