General Instructions
The USBN9602 is an integrated USB node controller that controls endpoint EP0 and six FIFOS, the other six are not recognized by USB specification version 1.0 and 1.1. Supporting USB interrupt, bulk and integration onto a single IC is the required USB transfer isochronous data transfer. 8-bit parallel interface receiver USB Endpoint (EP) FIFOS with 3.3V regulator, media access controller, port multiplexed and non-multiplexed CPU, a general purpose 8-bit parallel address/data bus. Programmable interrupt output Face Microwire/Plus interface and clock generation scheme allow the device to configure different interrupt tor. A total of seven FIFO buffers support different USB signaling requirements.

A bidirectional FIFO for forced configuration

Features Full Speed USB Node Device USB Transceiver 3.3V Signal Voltage Regulator 48 MHz Oscillator Circuit Programmable Clock Generator Serial Interface Engine Consists of Physical Layer Interface (PHY) and Media Access Controller (MAC), USB Compliant with Specification 1.0 Control/Status Register File USB Function Controller with seven FIFO-based endpoints:
– One bidirectional control endpoint 0 (8 bytes)
– Three transfer endpoints (2*32 and 1*64 bytes)
– Three receive endpoints (2*32 and 1*64 bytes) 8-bit parallel interface with two selectable modes – Non-multiplexed – Multiplexed (Intel compatible) DMAMicrowire/Plus 8482 supporting parallel interface ; Interface 28-pin SO package

Device overview
The USBN9602 is an integrated USB node controller. The USB standard specifies bit stuffing and offloading as the block diagram on page 1 of the datasheet shows the MA-A method to ensure an adequate transition on the wire to the device's chip components. The receiver clock is back to normal. Whenever a string of consecutive 1s of transceivers is encountered, the bit stuffing logic inserts 0s after every sixth in the data stream. The USBN9602 contains a high-speed transceiver whose bit debuffering logic reverses this process. Consists of three main functional blocks: Clock recovery block uses incoming nrzi data – Differential receiver extracts data from the derived input clock frequency) on-chip voltage reference. – Transmitter with on-chip current source, this clock is used for data recovery circuit. The output performance requirement that this transceiver meets is the binary data for this block (decoding from NRZI is described in Chapter 7 of the Universal Serial Bus Specification Flow), which can be properly sampled using Verification Version 1.0. Pulls a 12 MHz clock. Jitter performance and timing characteristics meet the requirements of Chapter 7. To minimize signal skew, the differential output swing is 7 of the USB specification. The transmitter is well balanced. Slew rate control is used by the driver to minimize radiated noise and speak across the 3.4 endpoint/control FIFO. The driver supports Tri-State operations to allow the Endpoint Pipe Controller (EPC) to provide bidirectional half-duplex operation of the interface transceiver. Used for USB functional endpoints. The end point is that the final differential sink operates on the complete data source or sink. Endpoint pipes are MON mode range, guaranteeing greater than data movement between USB and memory, and COMOF for single-ended receivers to avoid potential failures in the path between USB host and function.
Serial Interface Engine (SIE) behind a single-ended Ze-endpoint. According to the USB specification, up to 31 ROS such endpoint pipes are supported at any given time, each with the same functional address. The USBN9602, however, has single-ended receivers on both receivers and supports up to seven endpoint pipes. data line. With the exception of differential receivers, these are designed to detect absolute voltages through switches. The USB function is a USB device capable of transferring data.
The threshold is between 0.8V and 2.0V (TTL input). Receive external information on the bus. Functions may have NAL 1.5 ± 5% kW resistors connected to a voltage source between one or more configurations, each of which defines -3.0V and 3.6V referenced to local ground, and is the interface that makes up the device. Each interface, in turn, indicates on D+ that this is a high-speed node. Consists of one or more endpoints. Voltage Regulator (VREG) Each endpoint is an addressable entity on the USB that needs to respond to input and output tokens from the USB. The voltage regulator supplies 3.3V from the host (usually a PC). The In mark indicates the 5.0V device power supply for the host integrated transceiver. This has requested to receive information from the endpoint, the V output can be used to power 1.5KW, the output token indicates that the host is about to send a pull-up resistor. It can be disabled under Software Control Information for the endpoint.
This device is allowed to be used in 3.3V systems. This output must be decoupled with a 10 mF tantalum capacitor to ground when an IN token pointing to the endpoint is detected. The endpoint is responsible for responding to the small package with data. If the endpoint is currently stopped, the stop hand - Serial Interface Engine (SIE) shock packets are sent under software control. NAK (Negative Automatically Send iCal Layer Interface (PHY) Level and Media Access Acknowledge) handshake packet if the end USB Serial Interface Engine (SIE) consists of a physical point, enabled, but no data is present. Controller (Mac) level. PHY levels include digital - if the endpoint is isochronous and enabled, but no data clock recovery circuitry, a digital glitch filter, end of packet exists, a bit error after end of packet is detection circuitry, and bit stuffing and offloading logic. Sent on the bus.
The MAC layer includes the packet format, CRC Genera - again, upon detection of a send-to operation and check, endpoint address detection and pro-an endpoints, the endpoint is responsible for receiving to provide the necessary controls to provide NAKs, ACKs and ACKs sent by the host. packet and store it in a buffer. If the suspend response determined by endpoint control - the endpoint pipe is currently suspended, the suspend handshake specifies the LER of the endpoint pipe. SIE is also a response packet, sent at the end of data transfer. If Sible, which is used to detect and report endpoint pipe detection events, is currently disabled, no handshake packets are sent at the end of a data transfer for USB-specific events such as reset, suspend, and reconnect. If the endpoint Sumerian. The transmitter output of the module to the transfer tube is enabled, but there is no buffer to store. The receiver is well matched (less than 1ns) to minimize skew on the data, ie NAK (Negative Acknowledgement) handshake USB signals. Send packets. If the endpoint is isochronous and enabled but cannot process the data, the data is lost.

Disabled endpoints do not respond to In, Out, or 4.0 connection graph setup tokens.
The endpoint pipe controller maintains independent state and control information for each endpoint pipe. CS 1 28 CLKOUT For IN tokens, the endpoint pipe controller is responsible for transferring data from the defined buffer to the host. Road 2 27 Xout For the out token, the endpoint pipe controller is the response-wr/sk 3 26 xin for transferring data from the host to the defined buffer. INTR 4 25 mode microcontroller interface DRQ 5 24 mode 1 CPU or microcontroller can be connected via 8-bit DACK 6 23 GND.
Parallel interface or microwire interface. For the par-a0/ale/si 7 28-pin 22 VCC allel interface, there are two addressing modes (multiplexed or non-multiplexed). These modes are selected by D0/SO 8 SO 21 GND hardwired on Mode 1 and D1 9 20D to the correct binary code - Mode 0 pins. D2 10 19 days + In addition, interrupt output is provided. D3 11 18 v3.3 type high or low output active, or open drain low output interrupt programmable as push pull active - D4 12 17 AGND

PIN description
The following tables briefly describe the USBN9602 pins. A brief introduction to the PIN function. Each table lists a group of related devices and displays notes that do not require input or bidirectional devices. Device number, signal direction ("I" for input, O "Up or down as appropriate." This is the most important reduction. For output "I/O" for bidirectional, or nafor not applica-overall power consumption and limit emi .Power Supply Label Function Description Digital Power Supply (VCC)
23 NAGND Digital Power Supply (GND) NAAgnd Analog Power Supply (Agnd)
NAV3.3. Transceiver 3.3V voltage supply. This PIN can be used as an internal voltage regulator output. The regulator is limited to the internal transceiver and one external pulse. Years of external 1mm coupling capacitors are required at this point. The voltage regulator output is lossless on hardware reset. If the inner voltage regulator is left damaged, you can use this loose. as a 3.3V input transceiver. The Oscillator, Clock and Reset tabs feature description NAXin Input for Internal 48 MHz Crystal Oscillator Circuit. 3rd Harmonic Crystal 48 MHz can be used. The NAXOUT output is used for the internal crystal oscillator circuit. Second Clock Output This product provides a programmable clock source. Source on hardware reset: A 4 MHz Clock (probably a preliminary discontinuous phase). It may be programmed so that different speeds or decays through the clock configuration registers are synchronized and will appear smoothly. Reset active Low reset input provides signal conditioning on this pin to allow use of a simple power supply reset circuit

oscillator circuit
The Xin and Xout pins can be connected to a 48MHz closed-loop crystal oscillator. Alternatively, an external 48 MHz clock source can be input to the device. The internal crystal oscillator uses a 48 MHz 3rd xTAL1 harmonic crystal. Circuit showing Crystal options. If using an external clock source, connect it to XIN. Xout is not connected. It is possible that stray capacitance and inductance remain in the oscillator circuit. The trace length should be minimized by positioning the crystal and external components as close to the Xin and Xout pins as possible for C2.
NOTE: The circuit shown has been used from ECS Corporation only (eg part number ECS-480-S- 1-3OT). For other crystals, consult the manufacturer for recommended circuit and component values.
Third Harmonic Crystal Oscillator Connection

6.0 Parallel Interface The parallel interface allows the USBN9602 to operate as a 6.1 non-multiplexed mode. CPU or microcontroller peripherals. One of the two interfaces, the non-multiplexed mode uses the control pins CS, RD, the mode can be selected by the mode0 pin, while the wr, address pin a0 and the bidirectional data bus mode1 pin are pulled low. This mode is selected by Ty -- a non-multiplexed mode that connects the Mode 1 and Mode 0 pins to GND. – Multiplexing mode CPU directly accesses register data, data output and address read and write data USBN9602 can complete timing information about signal timing in standard mode or burst mode in non-multiplexed mode.

Standard Access Mode The standard usbn9602 access sequence of the address non-address register (addr) is used as a pointer to the inmultiplexed interface mode, i.e. writing the address to internal memory. This register is write-only, the address register is cleared, then data is read or written on reset. Data out/data out in registers. Data from the data output register occurs in the address register. The selection between the address registers and the data output register (data output) is done with the data output/data input register through the a0 memory register pointed to by the address register. enter. Updates occur under the following conditions: Burst Mode 1. In burst mode after the address register is written, the address register is written once with 2. The memory address of the desired on-chip register after reading from the data register. Then 3. Sequential read/writes to that register after writing the data in the register are read-only and save undefined data afterwards. Data Out/Data In registers, no need to write a new AD-reset. dressed. Data Output Register Contents for Read Operation - 6.1.6 Data Input Update options after each read. The data stored in the data input register (data_in) points to the user register that is written to the usbn9602 address. The table below provides an overview of the parallel internal - this register is write only and clears on reset. Face register for non-multiplexed mode. On the table, reserved bits return undefined data when read, should be 6.2 multiplexing mode. Write zero. Multiplexed mode uses control pins cs, rd, wr, address latch enable signal ALE and bidirectional

Access the register bit number address data bus this by connecting Mode 1 to GND and Mode 0 to VCC. Read data\address is latched into the address register at ALE. Write data input high, data output/input with the next active RD or WR signal. All registers are directly accessible in . Read reserved interface modes. Figure 7 shows the basic timing.

The USBN9602 supports DMA transfers, external Figure 8 shows the basic DMA read times, from endpoint 1 to 6 of the DMA controller. It shows basic DMA write times. mode, the device pins drq and dack are used in addition to the parallel interface pins rd or wr and data. DMA mode can only be used in parallel interface mode with DRQ (mode 1 is tied to GND). Read or write addresses are generated internally, and during a DMA cycle, the a0/ale pins are ignored. The DAC DMA support logic has lower priority than the parallel interface. During DMA cy-wr, CS needs to remain inactive. CLE If cs becomes active, the dack is ignored, and read/write operations are performed. Only one endpoint can be enabled at a given time to issue a DMA request to receive or transmit data when d[7:0] is entered.
To enable DMA transfers, the following steps must be performed: DMA writes to the USBN9602 local CPU to program the DMA controller for fast transitions through demand mode. In this mode, transfers occur only when requested by the USBN9602 via the DRQ pin. Data is read/written/written from the USBN9602 receive/transmit FIFO, and written/read from the local. memory during the same bus transaction.
The DMA address counter is programmed to point to the target memory block in the DRQ's local shared memory, and the byte count register is programmed with the number of bytes in the block to be transferred. Dack sets the DMA request enable bit and the DMA source bit. in the USBN9602. Additionally, software must set the respective endpoint enable bits for the RDs.
The USB host can now perform USB bulk or synchronous output transfers over the USB bus to the receive FIFO or D[7:0] data from the transmit FIFO in the USBN9602. If the warning limit of the FIFO is reached or the transfer/reception is complete, a DMA request/acknowledgement occurs to read the DMA pair from the USBN9602 for a predetermined number of start edge sequence bytes. The time at which a DMA request is issued depends on the selected DMA mode (by the dmacntrl.dmod bits), the current state of the endpoint FIFO, and the FIFO warning enable bits. DMA requests can be issued immediately.
After the DMA controller is granted bus control, it drives a valid memory address and asserts dack and rd or wr, thus transferring a byte from the usbn9602 receive FIFO to memory or from memory to transmit FIFO. This process continues until the DMA byte count, within the DMA controller, reaches zero.
After transferring the programmed amount of data, firmware needs to do one of the following (depending on transfer direction and mode): Queue new data for transfer by setting txcx.tx_en bit, set end packet by setting txcx.tx_last bit Flag, DMA transfers can be stopped at any time by setting the rxcx.rx en bit to re-enable reception, or to check if the last byte of the packet was received by resetting the USBN9602 DMA Request Enable bit. If the USBN9602DMA request enable bit is in the DMA cycle, the current cycle is terminated in the DMA request.
The Microwire/Plus interface allows the USBN9602 IRE/PLUS mode to use a serial pin called Chip Select (CS). Works as a peripheral to a CPU or microcontroller via a clock (sk), serial data input (si), and serial data output (so), such as a serial interface. Select this mode by pulling on the graph. Mode 1 pin is high and mode 0 pin is low. meager

The microwire interface is reset by the rising edge of cs. After the rising edge of sk, data on si is shifted in and data is shifted out. So after the falling edge of sk. The data transfer from and to the shift register is completed after the falling edge of the eighth. SK clock. Transfer data with MSB First Note: Writes to any register always read registers after the write occurs and shifts out that data in the next cycle. This read does not clear the bits in the respective registers, even when they are read. (cor) type drill. An exception occurred while writing to the TXDX (transmit data) register, which caused undefined data to be read in the next loop.

Device Functional Status At any given time, the USBN9602 operating in one of the USB specifications requires that the device must be ready. The following states: Respond to USB token or "nodereset" device reset reset within 10 ms of wakeup. "nodeoperation" ("nodeoperation" when the device is running) or -9.4 Function State Transition Mally State diagram of the device state "nodesuspend" when the device is suspended due to and transition. The condition that triggers each conversion is USB inactivity as shown. Conditions that require firmware "noderesume" are shown in italics when the device wakes up from operation. Note that all USBN9602 suspend state state transitions are initiated by firmware. Suspend, resume, or reset line conditions cause transitions from one operational state to another Operational status. These conditions are detected by specialized hardware and reported through the alternate event (Altev) register. If interrupts are enabled, an interrupt is generated when any of the specified conditions occur.
Suspending a USB device should be in response to a suspend event, which occurs at 3 ms and has elapsed without any detectable bus activity. The USBN9602 looks for this event and signals it by setting the altev.sd3 bit, causing an interrupt to be generated. The firmware should pass the USBN9602 into a suspend state.
In the suspend state, the transceiver enters a special low-power mode. All registered state and FIFO buffers remain static so that no additional action is required when activity is resumed. The USBN9602 can resume operation from a suspend state under firmware control as a response to a local event on the host controller, it can in turn wake up the USB bus through a remote resume operation, or signal when a resume command on the USB bus is detected Interrupt from the host controller.
Remote recovery If the host has enabled remote wake-up of this node, the USBN9602 can initiate remote wake-up. Once the firmware detects that the bus should be woken up, it releases the USBN9602 from the suspend state by initiating remote resume on the USB using the NFSR register. Node firmware must ensure that there is at least 5ms of idle time on the USB. A constant "k" is signaled to open the USB when in the resume state. This should last at least 1 ms, after which the USB host continues to send the resume signal for at least another 20 ms, and then completes the resume operation by issuing an end-of-packet (EOP) sequence. To successfully detect EOP, firmware must enter the "nodeOperation" state by setting the nfsr register. If no end packet is received from the host within 100ms , remote recovery should be initiated. Go through the software again.
USB Resume Operation When a resume or reset signal is detected in the suspend state, the USBN9602 can send this signal to the host system. Controlled by generating interrupts.

Firmware-Initiated Conversion

Node Functional State Diagram The following notes apply to the state diagram: – When the node is not in the nodeOperation state, all port registers and internal endpoint states are reset. – In noderesume state, the resume signal propagates upstream. – In the nodesuspend state, the node may enter a low power state capable of detecting a resume signal. The various conditions that trigger state transitions are described.

Endpoint action packets are broadcast from the root hub to all nodes, incoming USB packet address fields and endpoints. on a USB network. Address detection is implemented in fields extracted from the input bitstream. The hardware then allows the packet and to-address fields to be selectively received and compared with the functional address registers for optimal use of the microcontroller's bandwidth. A ter (fadr), if a match is detected, the endpoint field compares the function address with seven different endpoint combinations to all endpoint control registers. Operations are decoded in parallel. If a match is found, that match (epcx) is parallel. A match will cause the payload specific packet to be received into the FIFO; otherwise, it is ignored using the respective. Endpoint FIFO.

Endpoint 0 Operation If programming two endpoints in the same direction, please note that the actual current operating state is not directly with the same endpoint number, and both are enabled and visible to the firmware. Then, the data will be received or transmitted using the end-of-packet written to the FIFO if one is pointed at with a smaller number, until a dis-token for that endpoint is received. The packet remains in the FIFO in the event of an error capable of bulk or interrupted transfer, or detection of packet full. or the ISO transport is empty. For example, if you retry to receive EP2 and transmit with next-in token.
and receive EP4 both use endpoint 5, and can flush the FIFO contents to allow the responses to be all isochronous, then the first outgoing packet is the re-exit token, or write new data into the FIFO for the next receive EP2, the second Tokens are received for each output packet. Go to ep4, if there is no firmware interaction between the two. For ISO endpoints, this allows to implement a ping pong if an out token is received for the FIFO, the firmware will buffer the scheme and frame number matching log - only on the IC. No error conditions (crc or stuff errors). Erroneous receptions are automatically discarded. Endpoints in different directions with the same endpoint number still operate independently. 10.3 Transmit Endpoint FIFO Operation (Coefficient of Thermal Expansion 1, Coefficient of Thermal Expansion 2, Coefficient of Thermal Expansion 3) Bidirectional Control of Endpoint FIFO0 Operation Supported by Endpoints 1, 3 and 5 Bulk, Interrupt and Isochronous USB Transmit FIFOS Packets Two-way control. Therefore, firmEndpoint is zero. It can be configured to receive data sent to software and must update the FIFO content at the same time as the USB packet. By setting the DEF bit of the EPC0 ET to transmit the default address on the bus, the operation of the transmit FIFO does not support isochronous transfers.
Control endpoint. The Endpoint 0 FIFO can hold a single receive or transmit packet containing up to 8 bytes of data. A status diagram showing the basic operation of endpoint 0 uses FIFO for both receive and transmit directions.

The chart labels used in TX FIFO operation are interpreted as . Low. Transmit FIFO level. This value represents the number of bytes untransferred by the tfx to remain in the fifo before underrunning. Transmit FIFO x size. This is the total number of bytes that will occur the next time the FIFO is read. Available in FIFO. If txfl drops to TxRP specific value. Set the corresponding fvev.txwarnx bit if txfl is equal to or less than the transmit read pointer. This pointer is incremented in every txcx.tfwl. The time-first-in-first-out method for the endpoint controller to read data from the transfer. If tfx is 10.3.5 t counts, this pointer wraps to zero. achieve. The increment of TxRP will never exceed the value of the transmit FIFO count. This value indicates how many write pointers txwp have. Null bytes can be padded in the transfer If txrp is equal to txwp and fifo, an underrun condition occurs. Firmware can transfer more bytes by attempting to use the tx-txsx registers. cx. The last digit is not set. 10.4 Receive endpoint FIFO operations (RXFIFO1, 10.3.3 HWP RxFIFO2, RxFIFO3) transmit write pointers. This pointer is incremented for each receive FIFO that supports endpoints 2, 4, and 6. The time the firmware writes to the transmit FIFO. This pointer bulk, interrupt, and packet synchronous USB transfers wrap to zero if tfx is reached. greater than the FIFO size. If the packet length exceeds the FIFO size, the firmware must read the FIFO. If an attempt is made to write more bytes to the FIFO content while receiving a USB packet than is actually available (FIFO overflow), the write bus ignores the FIFO. So you should check t-count FIFOS. to get an indication of the number of empty bytes remaining.

RX FIFO operation FIFO warning can be issued if RXFL falls to A. Receive FIFO x size. This is the total number of specific byte values. Set the corresponding fvev.rxwarnx bit available in the FIFO. If RXFL is equal to or less than the rxcx.rfwl. file. RXRP recounts the receive read pointer. This pointer is incremented each time the firmware reads from the receive FIFO. This receive FIFO counts. This value indicates how many pointers will wrap to zero if RfXs are reached. RxRP is a byte that can be read from the receive FIFO. Never exceed the value of RXWP. Firmware can access this value via rfsx. register.
If an attempted read exceeds the number of bytes actually available (FIFO underrun), the last byte is read active for the repeti-10.5 programming model. Therefore, you should check rcount for the register hierarchy shown in Figure 19. It shows a re-indication of the number of bytes remaining received. Relationship between endpoint registers and event registers - Rxwp-ters. Receive write pointers. This pointer is incremented each time the endpoint controller writes to the receive FIFO. If Rfx is reached, this pointer wraps to zero. If rxrp is equal to rxwp and try to receive more bytes. Receive FIFO level. This value indicates how many more received bytes can be written to the FIFO the next time before an overflow condition occurs.