The CY2309SXC-1 is a low-cost 3.3V zero-delay buffer designed to distribute high-speed clocks in a 16-pin SOIC or TSSOP package. The CY2305SXC-1 is an 8-pin version of the CY2309. It accepts a reference input and outputs five low-skewed clocks. The -1H version of each device can run at up to 100-/133 MHz and drives higher than the -1 device. All devices have an on-chip PLL on the REF pin that locks to the input clock. The PLL feedback is on-chip and obtained from the CLKOUT pad. The CY2309 has two groups of four outputs, which can be controlled by select inputs, and BankB can be tri-stated if all output clocks are not required. Selecting the input also allows the input clock to be used directly for output purposes for chip and system testing.

There is no rising edge on the REF input when the CY2305 and CY2309 PLLs enter power-down mode. In this state, the output is tri-stated with the PLL off, resulting in less than 25.0 Ω current consumption for these parts. The CY2309 PLL as shown in Select Input, in another case turning off multiple CY2305 and CY2309 devices can accept the same input clock and distribute it. In this case, the deviation between the outputs guarantees that the power of the two devices is less than 700 ps. CY2305/CY2309 are available in two or three different product configurations, CY2305-1/CY2309-1 is the base part. The CY2305-1H/CY2309-1H is a high drive version of the -1, which has a much faster rise and fall time than the -1.

feature

10 MHz to 100/133 MHz operating range, compatible with CPU and PCI bus frequency

Zero input and output propagation delay

60 ps typical cycle-to-cycle jitter (high drive)

Multiple low-skew outputs

85ps typical output-to-output skew

One input drives five outputs (CY2305)

One input drives nine outputs, grouped as 4+4+1 (CY2309)

Compatible with Pentium-based systems

Test Pattern Bypass Phase Locked Loop (PLL) (CY2309)

Package:

8-pin, 150 mil SOIC package (CY2305)

16-pin 150 mil SOIC or 4.4 mm TSSOP (CY2309)

3.3 V operation

Commercial and Industrial Temperature Ranges

logical block diagram

8-Pin SOIC Pinout Diagram

Pin Description

Applicable to CY2305 pin signal description

1 REF[1] Input reference frequency, 5 V tolerant input

2 CLK2[2] Buffered clock output

3 CLK1[2] Buffered clock output

4 GND ground

5 CLK3[2] Buffered clock output

6 VDD 3.3 V power supply

7 CLK4[2] Buffered clock output

8 CLKOUT[2] Buffered clock output, internal feedback of this pin

16-Pin SOIC/TSSOP Pinout Diagram

Pin Description

Applicable to CY2309 pin signal description

1 REF[3] Input reference frequency, 5 V tolerant input

2 CLKA1[4] Buffered clock output, Bank A.

3 CLKA2[4] Buffered clock output, Bank A.

4 VDD 3.3 V power supply

5 GND ground

6 CLKB1[4] Buffered clock output, Bank B.

7 CLKB2[4] Buffered clock output, Bank B.

8 S2[5] select input, bit 2

9 S1[5] select input, bit 1

10 CLKB3[4] Buffered clock output, Bank B.

11 CLKB4[4] Buffered clock output, Bank B.

12 GND ground

13 VDD 3.3 V power supply

14 CLKA3 [4] Buffered clock output, Bank A.

15 CLKA4 [4] Buffered clock output, Bank A.

16 CLKOUT[4] Buffered output, internal feedback of this pin

Test Circuit #1

Test Circuit #2

Switching Characteristics

Applies to CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices Parameters [28] Description Conditions Min Typ Max Units

t1 output frequency 30 pF load 10 - 100 MHz 10 pF load 10 - 133.33 MHz

tDC duty cycle[29] = t2 ~ t1 measured at 1.4 V, Fout = 66.67 MHz 40.0 50.0 60.0%

tDC duty cycle[29] = t2 ~ t1 measured at 1.4 V, Fout < 50 MHz 45.0 50.0 55.0%

t3 rise time [29] measured between 0.8 V and 2.0 V - - 1.50 ns

t4 fall time [29] measured between 0.8 V and 2.0 V - - 1.50 ns

t5 output to output skew [29] All outputs equally loaded - 85 250 ps

t6A delay, REF rising edge to CLKOUT rising edge[29] Measured at VDD / 2 - - ± 350 ps

t6B delay, REF rising edge to CLKOUT rising edge[29] Measured at VDD/2. Measured in PLL bypass mode, CY2309 devices only. 1587ns

t7 device-to-device skew [29] Measured at VDD/2 on CLKOUT pin of device - - 700 ps

t8 output slew rate [29] measured between 0.8 V and 2.0 V using test circuit #21 - - V/ns

tJ cycle-to-cycle jitter [29] measured at 66.67 MHz, load output - 60200ps

tLOCK PLL lock time [29,30,31] Stable power supply, valid clock displayed on REF pin - - 1.0ms

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