Digital DC/DC PMBus 17A Module
ZL9117M function
The ZL9117M is a 17A, variable output, step-down fully digital switch-mode power supply PMBus compliant digital power supply. Included in the module for fast transient response is a high performance digital PWM controller, power MOSFETs, an inductor and an auto-compensating PID filter with all passive components required for a highly integrated DC/DC power solution. The external synchronization of this power module requires a manually compensated design effort. The ZL9117MP has a built-in automatic compensation algorithm that eliminates output voltage tracking and operates over a wide input voltage range, supports current sharing with an output voltage range of 0.6V to 3.6V, and can be set by programmable soft-start delay and ramp. The module is capable of supplying 17A. Only bulk inputs and external resistors or via PMBus. This high-efficiency power supply overcurrent/undercurrent protection requires an output capacitor to complete the design. Output PMBus compatible line, load, and temperature output voltage regulation voltages are precisely regulated to 0.6V over an application range of ±1%. Variety. Server, Telecom and Datacom ZL9117M features automatic compensation, internal soft-start, pre-biased output start-up capability for industrial and medical equipment.
Auto-recovery overcurrent protection, enable options, and general-purpose point-of-load ZL9117M are packaged in a thermally enhanced, compact package. (15mm x 15mm) and low profile (3.5mm) stamped QFNs are suitable for standard self-assembled package modules AN2034," in the ZL2004 and surface mount devices. The ZL9117M is RoHS compliant. The ZL2006" Figure 1 represents a typical implementation of the ZL9117M.
For PMBus operation, it is recommended to tie the enable pin (en) to SGND.

Typical Application - Single Module Notes:
5. If the PMBus master already has I2c pull-up resistors, then R1 and R2 are not needed.
6. When the DDC bus is shared with other modules, only one R3 is required per DDC bus.
7. The Vr, V25 , Vdrv and Vdd capacitors should be placed no more than 0.5cm away from the pins.
8. R4 is optional, but it is recommended to sink the possible ~100µA return current from the FB+ pin. Power is still available on the VDD pin only when the module is disabled.

Absolute Maximum Ratings (Note 9) Thermal Information
DC supply voltage for the VDD pin. …………….-0.3V to 15.7V Thermal Resistance (typ.) θja (°c/w) θjc (°c/w)
The input voltage of the VIN pin. …………-0.3V to 15.7V QFN package (Note 12, 13). ………… 11.5 Clause 2.2
MOSFET drive reference for VR pin. ………….-0.3V to 6.5V junction temperature. ……………..-55°C to +150°C
2.5 V logic reference for V25 pin. …………-0.3V to 3V storage temperature. …………-55°C to +150°C
MOSFET driver power supply for VDRV pin. ………….-0.3V to 7.5V lead-free reflow profile. …………See TB493
DDC logic I/O voltage, en, ESD level fb+, fb-, pg, sa, scl, sda, sync, vset pins. …………….-0.3V to 6V Recommended Operating Conditions Human Body Model (tested per JESD22-A114F). ………….2000V input supply voltage range, VIN. ………….4.5V to 13.2V machine models (tested per JESD22-A115C). ………….200V Controller Input Power, VDD (Note 10). ………4.5 volt to 13.2 volt live device models (tested per JESD22-C110D). ……1000V driver supply voltage, Vdrv. ………….4.5V to 6.5V lockout (tested per JESD78C; Class 2, Class A). …………100mA output voltage range, Vout (Note 11). ………….0.54V to 3.6V
Output current range, output (DC) (Note 24). …………0A to 17A
Operating Junction Temperature Range, Tj. ...-40°C to +125°C
CAUTION: Do not operate at or near listed maximum ratings for extended periods of time. Exposure to these conditions may adversely affect the product.
reliability and lead to failures not covered under warranty.
notes:
9. Voltage measured relative to sgnd.
10. VIN powers the FET. VDD powers the controller. VIN can be tied to VDD. For Vdd≤5.5V, Vdd should be connected to Vr.
11. Includes ±10% profit limit.
12. θJA was simulated in free air with the device mounted on a four-layer FR-4 test board (76.2 x 114.3 x 1.6 mm) with 80% coverage and 2oz cu on top and bottom.
Two, plus two, buried, one-ounce copper layers covering the entire test board area. Use multiple vias with a pass diameter = 0.3mm and a pitch of 1.2mm.
13. For θjc, the "box" temperature is measured at the center of the bottom of the package.

Function description table 1. Output Voltage Resistor Settings (continued) I2C/Smbus Communication The ZL9117M provides an I2C/Smbus digital interface, 1.80 61.9 allowing the user to configure all aspects of module operation and monitor input and output parameters. 1.90 68.1ZL9117M can be used with any I2C host device. Also, 2.00 75 As specified by smbus 2.0, modules are required on I2c/smbus to be compatible with smbus version 2.0. Pull-Up Resistors 2.10 82.5 Spec. The ZL9117M accepts most standard PMBus 2.20 90.9 commands. When using pmbus commands to control the device, 2.30 100 recommends that the enable pin be tied to SGND.
Only the smbus device address and vout_max are parameters that must be set by external pins. All other devices 2.80 121 parameters can be set via I2c/smbus. The device address is 3.00 133 is set using the SA pin. Vout_max is determined to be greater than 10% greater than the voltage set by the VSET pin. A standard 1% resistor value of 3.30 147 is used between the respective pins and sgn.
The output voltage can also be set to any value between 0.6V. Output voltage selection and 3.6V, the output voltage can be set to a voltage between 0.6V and the interface using PMBus commands via I2C/SMBus.
3.6V, provided the input voltage is higher than the desired voltage, and the RSET resistor program sets the output to the upper limit.
Output voltage at a value sufficient to prevent programming of the PMBus from setting the device voltage higher than it exceeds its maximum duty cycle specification. Resistance setting value. in Table 1. The RSET resistor is located on the VSET pin and the VSET pin is used to set the output voltage to the level indicated by the soft-start delay and ramp time.

It may be necessary to set a delayed reception from the enable signal until the output voltage starts to rise to the target. Output voltage resistor setting value. Additionally, the designer may wish to precisely set the time VOUT RSET (kΩ) required to ramp up to the target value after a delay has elapsed. These functions act as controls for the speed at which the loading IC is turned on. The ZL9117M provides overall control of delay and ramp time periods in the rush of current management strategies or several options that the system designer chooses precisely and independently.
The soft-start delay period begins when the en-pin is asserted. Ends when the delay time expires. Soft-start delay and ramp time are set to custom values via: i2c/smbus interface. When the delay time is set to 0 ms, the internal circuit is initialized (about 2 ms). The soft-start ramp period is set to 0 ms, and the output increases rapidly as the output load increases. Capacitor and loop settings allow. It is generally recommended to set the soft-start ramp to greater than 500 microseconds to prevent unexpected failures due to excess. electric shock. Power Good The ZL9117M provides a Power Good (PG) signal, indicating that the output voltage is level within the specified tolerance of its target without faults. By default, the pg pin is asserted if the output is within 10% of the target voltage. These restrictions and the polarity of the pins can be changed via I2C/SMBus.
The PG delay time is defined as the time from meeting all the conditions 1.60 51.1 for asserting PG in the ZL9117M to the PG pin. actually asserted. Usually this function is used instead of

Use an external reset controller to control external digital logic. synchronized with each other. One of the devices must have the zl9117m pg delay set equal to the soft start configured as the sync source by default, the rest of the devices must have the ramp time set. Therefore, if the soft-start ramp time is set to be configured as a sync input. Must use I2C/smbus 10ms, pg delay set to 10ms. The pg delay can be set to configure the sync pins. Independent of the soft-start ramp using I2c/SMBus. NOTE: Using the appropriate switching frequency and PLL PMBUS command will vary slightly from the value selected in . This difference is due to hardware quantization. ZL9117M integrates an internal phase-locked loop (PLL) for punching the internal circuit. The PLL can be driven by external loop compensation. The clock source is connected to the sync pin. When using the internal oscillator, the sync pin can be configured as a clock source. The ZL9117M operates as a voltage mode synchronous buck. A controller using a fixed frequency pulse width modulation scheme. The module is that if there is a clock signal, the oscillator of the ZL9117M will be internally compensated through the I2C/SMBus interface. Does not affect the FSW until the power supply (VDD) is turned off and on. boot sequence. Changes to the sync pin connections will be 571 kHz. The ZL9117M only exists when the internal switching frequency of the ZL9117M is the clock signal, and the ZL9117M will configure the switching frequency to list according to the status of the synchronization pins, such as synchronizing the rising edge of the external clock. If executed once after no incoming ramp, the auto-compensation gain is 50% and the power-good compensation period is asserted immediately after the first auto-start.
The ZL9117M has an automatic compensation function that measures the characteristics of the power train and calculates the tap coefficient. By default, auto compensation is configured as Table 2. Switching Frequency Selection Adaptive Diode Emulation Sync Pin Frequency Adaptive Diode Emulation Mode Turns off the low-side FET gate and drives it with a low load current to prevent the inductor current from going negative at 400kHz low, Reduced energy loss and overall increased open 571KHz efficiency. Diode emulation can be used for single-phase device resistors see Table 3 Note: When in diode emulation mode. A significant loading step is recommended before disabling diode emulation. If the user desires other frequencies not listed in the configuration, the switching frequency can also be set to any input undervoltage lockout using the I2c/SMBus interface with a value between 400kHz and 1MHz. Input undervoltage lockout (uvlo) prevents the ZL9117M from operating when the input falls below a preset threshold, indicating that the input supply is outside its specified range of synchronous resistance values. The uvlo threshold (Vuvlo) can be set between 2.85V and 16V using the rsync (kΩ) frequency (kHz) I2C/smbus interface. Or connected to SGND 400 in the event of an input undervoltage fault, the unit can respond in a number of ways: continue to operate without interruption.
Continue running for the given delay period and then shut down if the fault persists. The device is still on or turned off 571 until instructed to reboot. Shut down immediately until the fault is eliminated. This user can choose a specific number of retries. The default response to an 800 uvlo fault is to immediately shut down the module. The controller continuously checks for the presence of an 889 fault condition. The ZL9117M re-enables if the fault status is NO or longer connected to the V25 or VR 1000. Output overvoltage protection command, the internal circuit will select the switch. If use PMBus input value other than fsw=8MHz/n, ZL9117M provides internal output overvoltage protection frequency value Use n as an integer to realize a value circuit, this value circuit can be used for protection Sensitive load circuits are protected from approaching input values. For example, if you enter 810KH, you are subject to a voltage higher than its specified limit. A device will choose 800kHz (n=10). A hardware comparator is used to compare the actual output voltage (seen at the FB+ pin) to a threshold set above 15% higher than the target output voltage (default setting) when multiple Intersil digital devices are used together.

The voltage exceeds this threshold, the PG pin is de-asserted, and the controller can then respond in several ways: Immediate shutdown until the fault is cleared to turn off the high-side MOSFET and turn on the low-side MOSFET. The low-side MOSFET remains on until the device attempts to restart. The default response to an overvoltage fault is shutdown. The controller continuously checks for the presence of the device when the fault condition no longer exists and the device is re-enabled. For the external clock, the only allowed response is immediate shutdown. Output Pre-Bias Protection When voltage is present at the output of an externally applied power supply before power-up. The power control IC is enabled. Some applications require a pre-bias condition if the output is present during startup. The ZL9117M provides pre-bias protection during start-up output ramp. If the pre-bias is lower than the target voltage, the pre-configured delay period has elapsed, the target voltage has been set to match the existing pre-bias, and the output of the pre-bias responds to the adjusted value at the pre-configured ramp rate. enable. If the pre-bias voltage is higher than the target voltage, the output voltage will transition linearly to the final value. The pre-configured delay period has elapsed, the target voltage has been set, and the actual time it takes for the output to go from pre-bias to match the existing pre-bias, both drivers are target voltages. PWM duty cycle enabled pre-bias. However, the total time from delay pre-bias.
Period expires, when the output reaches its target value, once the pre-configured soft-start ramp period expires, the PG pin is asserted (assuming the pre-bias is not higher than the overvoltage limit). Then, PWM adjusts its duty cycle to match the original target voltage, and the output drops to the preconfigured output voltage. If a pre-bias voltage above the overvoltage limit exists, the device does not initiate an open sequence and declares an overvoltage fault condition. In this case, the response of the device based on the output overvoltage fault response method has been selected. See "Output Overvoltage Protection" on note, no pre-bias protection is provided for current sharing. Tracked groups are also enabled. VDD must be tied to VIN for proper pre-bias start-up in single module operation. Output overcurrent protection
The ZL9117M can protect the power supply from damage if the output is shorted to ground or an overload condition is imposed on the output. The following overcurrent protection response options are available

Phase Extension B. Orbit 100% VTRK Ltd. Member track input power, the clock phase offset needs to be adjusted when multiple load converters share a common DC reference at the instantaneous voltage value applied to the VTRK pin, for each device, so that not all devices start switching in a consistent track At different points in time, the input simultaneously can be greatly reduced. Set each converter to start its switching loop rail at 100% VOUT limit vref>vm em vref vm emVref=1.8 Volts capacitance requirement and efficiency penalty. Because the peak tly toff dly vmem=0.9v 0 the current drawn from the input supply is effectively distributed across en. A reduction in power loss proportional to IRMS is a period of time where the peak current at any given moment is limited drastically reduced. Vref=1.8V To enable phase spreading, all converters must be synchronized en to the same switching clock. The phase offset of each device can also be set to any value between 0° and 360 ° in 22.5°. Incremented via i2c/smbus interface. Coincident Tracking Output Voltage Tracking Ratio: This mode configures the ZL9117M as a ramp for high performance systems that place stringent requirements on sequential output voltage, turning it on as the supply voltage applied to it. This is especially the VTRK pin. The default setting is 50%, but different traces can be configured using the pmbus command with external resistors or when powering fpgas, asics and other advanced processors. Devices that require multiple supply voltages to power a single ratio. die. In most cases, the I/O interface runs on the higher voltage A. rail limited by 50% VOUT. Member track Therefore, the core supply voltage must not refer to the track and stop when the member reaches it.
Exceeds the I/O supply voltage specification by 50% of the target voltage provided by the manufacturer. Voltage tracking protects these sensitive ICs by limiting the differential voltage across multiple sources B. Orbits are limited to 50% VTRK. Member tracks are in a power-up and power-down sequence. The reference value when applying the instantaneous voltage value to the VTRK pin until the component rail reaches the ZL9117M integrates a lossless tracking scheme that allows the reference rail voltage, or if the component is its output to track the voltage applied to the VTRK pin, configured low at 50% of the reference voltage. No other components are required. The vtrk pin is an analog member that will achieve the goals of its configuration, input when tracking mode is enabled, and output regulation of the member device. The voltage applied to the VTRK pin, used as rail voltage tracking can only be configured through the PMBus. For example, Vref=1.8VVmem=0.9V The ZL9117M offers two tracking modes: Coincident and a set of digital DC modules or devices that can be configured for proportional metering. The predetermined sequence states that the output voltages are powered up. This feature is especially useful for the waveforms of the two tracking modes. Useful when powering advanced processors, FPGAs and ASICs Coincidence: This mode configures the ZL9117M to have another supply ramp up to its operating voltage to avoid needing a supply to reach its operating voltage; The rate of voltage on the same. Sequencing of multiple devices can be achieved by configuring the VTRK pins. There are two options for this mode: each device via I2C/smbus interface.
A. 100% VOUT LTD track. A member track configures a sequence of multiple devices by issuing a PMBus reference track, stopping when a member reaches a command to assign its target voltage in the sequence, chain, and devices following in the sequence chain. The enable pins of all devices in the sequence group must be bound together to drive up to start the group. ENABLE must be driven low to initiate a sequential shutdown. team member.
Refer to Fault Expansion-R digital DC modules and devices that can be configured to broadcast fault events from vmembers to other devices in the group via the DDC bus. -R When a non-destructive fault occurs and the device is configured to shut down in the event of a fault, the device will shut down and broadcast a fault event on the DDC bus. Other devices on the DDC bus down at the same time and attempt to restart in the specified order (if configured to do so). Active Current Sharing Module Input Reference Paralleling multiple ZL9117M modules can be used to increase the active current sharing output current capability of a single power rail, for loadlines with the same slope, connect the DDC pins of each module together and connect the component voltage Configured to the reference voltage, the module acts as a current sharing rail and the cells share the current, thereby closing the gap between the inductor currents. Also within a few percent. Figure 17 illustrates a typical two-module connection. The reference current to voltage relationship is given by Equation 2 where r is the value of the droop resistance. DDC ZL9117M The ishare_config command is used to configure the module cout for active current sharing. The default setting is independent non-current sharing modules. The current shared track can be a system ordered group. CIN For the failure configuration, the current shared rail configuration is in quasi-redundant mode. In this mode, when one member module DDC ZL9117M VOUT fails, the remaining members continue to operate and try to maintain regulations. Among the remaining modules, the module with the lowest member position becomes the reference. If fault extension is enabled, the current shared track fault is not broadcast by the current shared group until the entire current shared track is faulted. A sharing technology that balances the unbalanced output of the module by aligning the load line of the component module with the reference line
The ZL9117M uses a low bandwidth, first-order digital current, and the phase offset of the multiphase current-sharing module is automatically set within 22.5° to a value increment between 0° and 337.5° as shown in Equation 3:
module. Phase offset smbus address 4:0 = – current (equation 3) common position 22.5 droop resistance Voltage path for adding artificial resistance to the output to control the slope of the load line curve, please refer to application note AN2034 for more details Calibration due to power supply Physical parasitic mismatch due to current sharing. Train components and printed circuit board layout. When the system starts, the module with the lowest member phase is added/removed. The position selected in the ishare_config is defined as zl9117m to allow multiple power converters to be connected. Reference module. The remaining modules are members. The load current of the paralleled power supply is higher than the solvable load current. The reference module broadcasts its current through the DDC bus. Single-phase design. In doing so, the power converter is a member using the reference current information to adjust its optimum value over the range of load currents required for all phases. voltage (Vmember) to balance the current load for each operation. During light loads this can be beneficial. modules in the system. Disabling one or more phases removes the switching losses associated with the current consumption of those phases, resulting in higher efficiency.

The ZL9117M provides the use of PMBUS commands in response to observed load current changes to power well before the current shared rail ramp. Any member of the current shared track of data can be deleted. If the value says that the referenced module is removed, the 1 remaining active module copies the current snapshot value from flash to the lowest member location which will become the new reference. RAM for instant access using the snapshot command. Also, any change to the current number of members of 2 will write the current snapshot value to flash. Shared rails will speed up automatic phase distribution within the available range only when the device is disabled. All active phases readjust their phase positions for tracks based on the order within the number of active members. It should be noted that the VDD voltage of the device must be as high as 1400 microseconds in the process of writing data to the device if the current member of the shared rail is forced to shut down the flash. This is not desirable due to the observed failure, if the VDD supply of the device drops below all orbital members trying to get the result may be observed. After troubleshooting, reboot at the same time. 3.0V during the process. The following procedure is recommended for monitoring via i2c/smbus: Snapshot parameter capture after failure: The system controller can monitor various zl9117m system parameters via the I2c/smbus interface. 1. Configure the module with a configuration file (optional) The module can monitor any number of power transitions. Parameters include but are not limited to: enable snapshot mode by setting bit 1 of the misc-config command to 1. This can be done before or after the module is enabled. NOTE: DO NOT STORE OTHER CONFIGURATIONS • Input Voltage/Output Voltage Settings in Default/User Storage.
• Output current 3. At this point, the module starts capturing parameters in RAM that are operational for snapshots, in every firmware cycle. • Internal temperature 4. The module is configured to capture operational parameters.
• The switching frequency after a fault occurs during operation.
• Duty cycle 5. After a fault occurs, set it to 0 by setting the misc_config command. This is to prevent firmware from capturing snapshot parameters with current values from post-fault update RAM values. ZL9117M provides a special function that users can use 6. Disable modules. Capture parameter data after normal operation or 7. Send snapshot control command 1 to read stored errors. The snapshot function is enabled by setting data bit 1 in flash to RAM at any time. Issue the Amisc-config command set to 1. The snapshot feature allows snapshot commands to read data from RAM via smbus. a period of time. It should be noted that reading 32 bytes takes up the smbus minibus. This can be done during normal operation, although the user reads parameters via an 8-block read transfer. Repeat step 7 to disable in the misc-config command. power cycle. Make sure the snapshot mode is Snapshot control commands that allow users to store non-volatile memory and the flash snapshot parameters of the device security response function data from flash memory, two conditions must be met: the memory after a failure. In order to read stored pending faults, as well as read stored data from flash memory the user can only restore the module to the ZL9117M which has internal non-volatile memory where the user stores the configuration. Comprehensive security measures ensure
1. Modules should be disabled. provided to them.
2. Snapshot mode should be disabled by changing bit 1 during initialization, zl9117m checks stored other configuration as 0. This is to prevent the firmware from updating the values contained in its internal non-volatile memory. The RAM value after this failure is the same as the current value. ZL9117M provides two memory storage units to describe the usage of snapshot control commands. User access is as follows: Specific Fault Conditions). The response to a specific fault is a shutdown (write to flash if the device is configured to automatically write to flash after a fault if the device is configured to trigger 1 when any fault threshold level is exceeded. Default storage: The default configuration of the zl9117m is to restore on smbus by issuing \ u default \all command. Stored in the controller's default store. Modules can
2. User Storage: Some power settings can be modified by the user as described in this data sheet. Users store their configuration in the user store.

The output capacitor selects the current and can cause premature failure. There are also several trade-offs that must be considered when choosing an X7R or X5R dielectric with low ESR and a maximum of 1.1X for ceramic capacitors. output capacitor. A low ESR value is recommended for smaller expected input voltages. Output Deviation Output Voltage Ripple (Vorip) at Transient Load Steps (Vosag) and Low Steps. However, low ESR capacitors, layout guidelines using high capacitance devices and low ESR combined capacitance values are also relatively low. Many designs can e.g. semi-stable (X5R and X7R) dielectric ceramic capacitors, performance some layout considerations are necessary. To achieve stable operation, low loss, and good thermal performance equipment in parallel. • Establish separate ground plane output current values for sgnd (pin 9) and pgnd. The rise or fall of the inductor current to the new steady state is required to minimize the output voltage deviation instantaneous load steps, and the relatively large capacitance results in a large output voltage ripple. Likewise, on the upper layer for high ripple current, low capacitance values lead to A (pin 10 and pin 16) and connect them at one point cv25, cvr, rsa and rvset are placed on the bottom layer and connected to a single point connected to SGND plane for PGND. This will help prevent high frequency noise from getting sent to the controller via SGND.
• Place a high frequency ceramic capacitor between (1) VIN and (2) as a starting point to output ripple pgnd (pin 16), (2) half of VOUT and pgnd (pin 16) and (3) bypass voltage Assign to capacitor ESR and assign the other half to capacitors as capacitors between vdrv, vdd, v25, vr and the ground plane as shown in equations 4 and 5: close to minimize module noise at high frequencies. High-frequency ceramic capacitors (Equation 5) close to the module with multiple vias to connect the power planes in different layers. Minimize conduction losses and thermal stress • Connect telemetry traces to regulation points, use these values for initial capacitor selection, use A for tight output voltage regulation, and keep it in a single capacitor or multiple capacitors in parallel. parallel. The path trace from FB- to a location near the load after selecting the capacitor produces an output voltage to ground, and a trace from FB+ to the point of load, where the ripple can be calculated with Equation 6: A tight output voltage is required. (Equation 6) • Avoid routing any sensitive signal traces such as VOUT, FB+, FB- near the sensing point of the phase pins.
Since each part of this equation is less than or equal to half of the allowable output ripple voltage, Vorip should rsa be less than the desired maximum output ripple. SGND is therefore recommended to use a combination of several ceramics. Usually, at higher output voltages, the ripple current of the inductor is very large.
Ripple Voltage and Loop Stability. Insufficient number of capacitors with low ESR bulk capacitors to ensure low output CVDD VDD 12 19 FB+VOUT Capacitance at the output causes control CVDRV 13 VDRV 18 FB-to unstable cycling. Load Ground Input Capacitor 14V 17 Vin A dedicated input capacitor of 15V is highly recommended for any point-of-load design, even if the power supply is PGND powered by a heavily filtered 5V or 12V "bulk" off-line power supply. This is due to the high rms ripple CIN current produced by the buck converter topology. This ripple suggests layout currents will flow through the supply bus and return to the plane, with no capacitive filtering near the power circuits, a thermal consideration that couples noise into other system circuits. The input capacitor heat loss versus θja rating should be 1.2 times. The ripple current calculated in the modeling analysis of Equation 7 can be used to evaluate the thermal in order to avoid overheating of the capacitor due to the high ripple of the module. The derating curve is derived to keep the

Temperatures below the maximum bonding temperature of the stencil pattern are shown on the second page of the package.
+125°C. In practice, other heat sources and design profiles on page 58. 15x15. Gap width should take margin into account. Pad to pad is 0.6mm. The user should consider the entire stencil pattern when designing its pad. Laser Cut, Packaging Instructions Stainless Steel Template ZL9117M with Electropolished Trapezoidal Walls The construction of the ZL9117M is a recommended quad flat pack. Electropolished "smooth" hole wall lead-free package (QFN). This packaging has the advantage of reduced surface friction and better slurry release. Such as good thermal and electrical conductivity, light weight and reduce voids. Use trapezoidal section aperture (TSA) for small volume. QFN packaging is suitable for surface mounting and promotes paste release, creating a "brick-like" paste deposit. technology and easier to use in industry. Assists with the placement of fixed parts. The 0.1mm to 0.15mm template ZL9117M contains many types of devices, including resistors, and the thickness is recommended for this large pitch (1.3mm) QFN. Lead frame package with exposed copper thermal pads, capacitors, inductors and control ICs. ZL9117M is the copper reflow parameter. Has good electrical and thermal conductivity. Due to the low mounting height of the QFN, the copper for "dirty" solder Type 3 is paste overmolded for leadframes and multi-part assemblies as recommended by ANSI/J-STD-005. A nitrogen purge protects the polymer molding compound of these devices. Also recommended for reflow. A typical stencil pattern design for a system board reflow profile module is shown on page 2. The package outline and typical printed circuit board layout pattern design is 15mm x 15mm x 3.5mm. Typical reflow profile parameters. These guidelines are generic and tailored for different production practices.
Depends on the thermal mass of the entire filler plate, so not suitable for QFN only. Sectional drawings are given as a guide for design rules. Users can customize according to their own applications.
300 Peak temperature ~ +245°C; typically 60s-150s above +217°C PCB Layout Pattern Design 250 Keep below 30s within 5°C of peak temperature. The bottom of the ZL9117M is a lead frame, which is connected to the printed circuit board by a surface mount process. The PCB 200 slow ramp (3°C/s max) layout mode is shown on the second page of the package with a immersion temperature of +150°C. The PCB layout mode is 150 to +200°C for 60s~180s.
Essentially 1:1 with QFN exposed pads and I/O termination dimensions, except the PCB ground is slightly extended by 100 0.2mm (0.4mm max) longer than the QFN termination, allowing at ramp rates (from +70°C to +90°C is 1.5°C) around the solder fillet. perimeter of the package. This ensures a more complete and 50 inspectable welded joint. The thermal landing should match 1:1 with the package exposed die pads on the PCB layout. Thermal Via Duration (s) A grid of thermal vias with 1.0mm to 1.2mm pitch, this grid. Typical reflow profile and connection with buried copper plane should be placed in hot soil. Through holes should be 0.3 mm to 0.33 mm in. 1.0 oz diameter copper barrel. Although adding more vias (by reducing via spacing) will improve thermal performance, diminishing returns will be seen as adding more and more vias. Just use the size and board design rules applicable to the thermal ground allow.
The reflow solder joints on the I/O pads around the stencil pattern design should have a standoff height of approximately 50 to 75 microns (2 mm to 3 mm). Solder paste stencil design is the first step in optimizing the development of reliable solder joints. The ratio of die aperture to pad size should typically be 1:1. The aperture width can be slightly reduced. Helps prevent solder bridging between adjacent I/O grounds. Reducing solder paste volume in larger thermal pads recommends using a small aperture array instead of a large aperture. It is recommended to use a stencil printing area of 50% to 80% of the printed circuit board layout pattern. typical solder