The HIP6601B , HIP6603B and HIP6604B are high frequency, dual MOSFET drivers specifically designed to drive two power N-channel MOSFETs in a synchronous rectified buck converter topology. These drivers combine with the HIP63xx or ISL65xx family of multiphase step-down PWM controllers and MOSFETs to form a complete core-advanced microprocessor voltage regulator solution. The HIP6601B drives the lower gate with a synchronous rectifier to 12V, while the upper gate can be independently driven over a range of 5V to 12V. The upper and lower gates of the HIP6603B driver are in a range of 5V to 12V. This flexibility of driving voltage offers the application of optimized advantages involving the trade-off between switching losses and conduction losses. The HIP6604B can be configured as either the HIP6601B or the HIP6603B. The HIP6601B, HIP6603B output drivers and HIP6604B have high-efficiency switching power supply capacity MOSFETs operating at frequencies up to 2MHz. Each driver is capable of driving a 3000pF load with 30ns propagation delay and 50ns transition time. These products implement only an external bootstrap capacitor requirement on the upper gate. This reduces implementation complexity and allows the use of higher performance, cost-effective, N-channel MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from turning on simultaneously.

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Designed for versatility and speed, the HIP6601B, HIP6603B, and HIP6604B are dual MOSFET drivers that simultaneously control the high-side and provide PWM signals externally from a low-side N-channel FET. The upper and lower gates are held low until the driver is initialized. Once the VCC voltage exceeds the VCC rising threshold (see Electrical Specifications), the PWM signal uses gate transition control. Turning off the lower MOSFET is initiated at the rising edge of PWM. After a short propagation delay [TpdlLGATE], the lower gate starts to drop. Typical Fall Time [TFLGATE] is provided in the Electrical Specifications section. The adaptive shoot-through circuit monitors the LGATE voltage and determines the gate delay time [TPDHUGATE] based on how fast the LGATE voltage falls below 2.2V. This prevents both the lower and upper parts from going on simultaneously or punch-through of the MOSFET. Once this delay period is complete the upper gate drive begins to rise [t Rugate] and the upper MOSFET turns on.

Three-state PWM input

A great feature of the HIP660X driver is the addition of a window-closing PWM input. If the PWM signal enters and remains within the turn-off window for a set of holdoff times, the output drivers are disabled and both MOSFET gates are pulled low and held low. Closes the window when movement other than the PWM signal is removed in the shutdown state. Otherwise, the PWM rising and falling edge thresholds outline the electrical specification DETERMINE when the upper and lower gates are enabled.

Adaptive penetration protection

Both drivers combine adaptive shoot-through protection to prevent both high-side and low-side MOSFETs from turning on while reducing the input power supply. This is to ensure that the drop gate has finished turning off 1 before another MOSFET can be raised. During turn-off of the lower MOSFET, the LGATE voltage is monitored until it reaches a 2.2V threshold, at which time the UGATE release rises. UGATE turns off the phase voltage during adaptive shoot-through monitoring. Once the phase has dropped below the 0.5V threshold, LGATE can be raised. The rise time of the lower gate is monitored during the phase duration. If the phase has not dropped below 0.5V within 250ns, LGATE is pulled high to keep the bootstrap capacitor charged. If the phase voltage exceeds the 0.5V threshold during this period and remains high for longer than 2µs, LGATE transitions low. The upper and lower gates are then held low until the next rising edge of the PWM signal.

Power-on reset (POR) function

During initial startup, the VCC voltage rise is monitored and the gate driver remains low until a typical VCC rise threshold of 9.95V is reached. Once the VCC rising threshold is exceeded, the PWM input signal takes the control driver of the gate. If VCC falls below the typical VCC falling threshold of 7.6V during operation, then both gate drivers remain low again. This condition exists until the VCC voltage exceeds the VCC rising threshold.

Power consumption

Package power dissipation is primarily a function of switching frequency and the total gate charge of the selected MOSFET. Calculating power consumption in drivers is a desirable application that is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the recommended maximum operating junction temperature of 125°C. The maximum allowable IC power dissipation for the SO8 package is approximately 800mW. When designing a driver into an application, it is recommended that the following calculations be performed to ensure the desired safe operating frequency for the selected MOSFET. Power dissipation by the driver is approximated as:

where fsw is the switching frequency of the PWM signal. VU and VL represent the upper and lower gate rail voltages. QU and QL at the upper and lower gate charges are determined by the selection of the MOSFET and any external capacitors added to the gate pin. In my DDQVCC product the static power consumption of the driver and typically 30mW. The power dissipation is approximately the result of the power transferred to and from the upper and lower gates. However, the internal bootstrap device also consumes power on the chip during this refresh cycle. In terms of expression this power supply is lower than the total gate charge of the upper MOSFET explained. When booting the device, the low-side MOSFET or its body diode conducts and pulls toward the PHASE node GND. While the bootstrap device is on, the current path is the refreshed bootstrap capacitor formed. The bootstrap capacitor is equivalent to the total gate charge of the field effect transistor since the charge taken from the upper gate drive MOSFET is taken out. Therefore, the required refresh power bootstrap capacitance is equivalent to the gate capacitance used to power the MOSFET.

power and frequency