Functional Description Low-Power CMOS Technology Microchip Technology Inc. 93XX86A/B/C Devices Word-Sized ORG Pin Selected for "86C" Version 16K-bit Low-Voltage Serial Electrically Erasable
2048 x 8-bit Organization "A" device (unorganized) PROM (EEPROM). word optional devices such as
The 1024 x 16-bit organization "B" device (unorganized) 93XX86C relies on an external logic driver organization pin to set the level of word size. For 8226 ; program enable pin write protects entire dedicated 8-bit communication, array of 93XX86A devices available, while 93XX86B devices offer self-timed erase/write cycles (including dedicated 16-bit communication, available on SOT-23 ) only autowipe) device. The Program Enable (PE) pin allows automatic generation of a General before wral user to write-protect the entire memory array.
Power On/Off Data Protection Circuitry Advanced CMOS technology makes these devices industry standard 3-wire serial I/O for low power, nonvolatile memory applications. The entire 93xx family is available in standard packages - Device status signals (ready/busy) including 8-wire PDIP and SOIC, and advanced sequential read function packages including 8-lead MSOP, 6-lead SOT-23,
1,000,000 E/W cycles and 8-lead TSSOP. Lead-free (pure matte tin) finish data retention > 200 years.
Supported temperature range:
- Industrial (I) -40°C to +85°C package type (not to scale)
-Automotive (E) -40°C to +125°C PDIP/SOIC

Electrical Characteristics Absolute Maximum Ratings) VCC 7.0V All Inputs and Outputs wrtvss -0.6V to VCC+1.0V Storage Temperature -65°C to +150°C Power-Up Ambient Temperature value" of stress may be on the device. This is only a stress rating and the functional operation of the device under the above conditions or any other conditions.
What is shown in the action list of this specification is not implied. Exposure to maximum rated conditions for extended periods of time may affect device reliability.

Data for function description data (di/pause/DO)
When the Oxford pin is connected to *ICE's VCC (X16), it is possible to connect both the DATA and DATA-OUT pins to organize the selected ICE. when it is connected together. However, and it is possible to configure information for the selected tissue on the ground ice (x8). instruction, a "two-occur bus conflict" in "virtual zero." Address and data write in the end is clocked.......precedes the read operation of the pin, if it is a logic high A0The rising edge of the clock (CLK). Ice level at DO pin. Voltage levels in such a state to see normally successfully in a high impedance state, when I read the data of undefined and ice will be in The preparation of the ice indicates equipment. You will enter 'High Z State' on edge drop CS. 2.3 Data Protection Typical Conditioning A Startup Voltage (1.5V for 93aa' 93lc devices in all operating modes, VCC is inhibited below the Ice detected start bit device, if CS and bottom are 3.8V 93C devices.
Gordon is on the positive edge of the clock's Irvine and EWDS commands to provide additional firsts. For accidental programming, the protection is detected at the beginning of the AC ICE, CS, CLK, II, and normal operation.
In any possible change (except for one of these two combinations Note: add protection, EWDS command to start the conditioner), no resulting in any device should be performed after every write operation (read, write, erase, hit, EWDS operation). eral or wral). As long as the CS is high on ice, the ice device has no language and is in standby mode. After power up, the ice automatic device
EWDS mode. Therefore, even if an instruction must follow an instruction to start the conditioner will be read-only performed before the initial erase or write instruction if the desired opcode, address and data bits can be executed.

The erase do-pin indicates all data bits that are forced low (TCSL) for the device erase command if CS goes high after at least 250 ns. The do at logic "0" represents the specified address for programming the logic "1" state. The ascent is still in progress. Do at logic "1" indicates that the register at the specified address has been erased before the edge of CLK begins the last address bit, and the write cycle. The device is ready to accept another command.
Note: issuing a start bit and then driving cs low will clear the ready/busy state

The clear all (general purpose) DO pin indicates to the device that the clear all (ERAL) instruction will clear the entire low (TCSL) if CS goes high after at least 250 ns. The memory array is in logic "1" state. A parenteral loop is the same as an erase cycle, with a different note: emit a start bit, then make the cs low opcode. Fully automatic loops are fully automatically timed. Will clear the ready/busy state on the rising edge of CLK before the last data bit initiates DO.
write cycle. The clock to the CLK pin does not require VCC to be greater than or equal to 4.5 V for normal operation.

RASE/WRITE disable and enable (EWDS/EWEN)
The 93XX86A/B/C are powered up during the erase/write process to prevent accidental data disturbance, disabled (EWDS) state. All programming modes must be an EWDS instruction, which can be used to disable all erase/write functions preceded by an Erase/Write Enable (EWEN) instruction-write function, which should follow all programming tions. Once the EWEN instruction is executed, the program operates. The execution of the read instruction is such that Ming remains enabled until the EWDS instruction is independent of the EWN and EWDS instructions.
Executed or VCC has been removed from the device.

read device) output string. The output data bit will be turned on
The rising edge of CLK is stable after specification, and the read command outputs serial data with time delay (TPD). Sequential reads are possible when addressing memory locations on the DO pin. A virtual CS is held aloft. Memory data will automatically cycle 0 bit before 8 bit (if ORG pin is low or A version to next register and output in order). device) or 16-bit (if Org Pin is high or B version

A write to the do-pin instructs the device, if cs goes high after at least 250 ns, the write instruction is followed by 8 bits (if org is low (tcsl). do at logic '0' indicates programming low or a version A device) or 16 bit (still in progress if the org pin is high. A do on a logic '1' indicates that the or b version of the data written to the register at the specified address has been written to the device using the specified address. Started by the rising edge of the CLK instruction Timed to automatically erase and specify data and the device is ready for another programming cycle.
on the last data bit.
Note: issuing a start bit and then taking cs low will clear the ready/busy state from the write all (wral) do pin to instruct the device if cs goes high after at least 250 ns, the write all (wral) instruction will write The whole low bit (tcsl). An in-memory array with the data specified in the command. The auto-timed auto-erase and program cycle is: issue a start bit, then bring cs low on the last data bit initiated by the rising edge of CLK. There is no need to clock the CLK pin after clearing the ready/busy state is complete.
The device has entered a wrap loop. Wral VCC must be greater than or equal to 4.5 V for proper operation. Commands include automatic general-purpose loop devices. Therefore, the wral instruction does not require a generic instruction

Chip Select (CS) 3.3 Data Input (DI) High level selects the device; low level deselects (DI) for data in the start bit, opcode clock. device and force it into standby mode. However, the address and data are synchronized with the CLK input.
An ongoing programming cycle will be complete regardless of the Chip Select (CS) input 3.4 Data Out (DO) signal. If CS is driven low for one program cycle, the device will enter standby mode once data is output using the data output (DO) in read mode. The programming cycle is complete. Synchronized to CLK input (TPD after POSIC must be 250 ns low (TCSL) between active edges of CLK).
continuous instruction. Internally this pin also provides ready/busy status information if cs is low and the control logic remains in reset. operations during erase and write cycles. Ready/busy status information can be found on the do-pin, if cs is the serial clock (CLK) goes high and low after minimum chip select low time (TCSL) and erase or write operations Serial clock is used to synchronize started communication.
Positive between the master and the 93xx series, if CS is held, the status signal is not available on DO. The opcode, address, and data bits are clocked low throughout the erase or write cycle. Here, on the positive edge of CLK. In the case of the data bit is also a clock, do is in high-z mode. If the state is checked out on the positive edge of CLK. After an erase/write cycle, the data line will go high
CLK can be stopped at any point in the transmission to indicate that the device is ready. Sequential (at high or low level) and can continue to pay attention: issue a start bit, then set cs low at any time of clock high time (tckh) and slave clock low time (TCKL). This enables the control host to execute.
Freely prepare opcodes, addresses and data.
CLK is a "don't care" if CS is low (device deselected). If organization (Organization, Organization, Organization, Organization, Organization) cs is high, but the start condition has not yet been detected (di = 0), any number of clock cycles when the ORG pin is tied to VCC or logic HI can be controlled by the device Receive without changing its state (i.e. select (x16) memory organization). when the organization waits for a start condition). The pins are connected to VSS or logic LO of the (x8) memory. CLK cycle write (ie, autoerase/write) cycles are not required during self-timing. Organization selected. To operate correctly, organizations must be bound to a valid logical level.
The specified number of digital clock cycles (respectively, 93XX86A devices are always x8 organization and 93XX86B devices are always x16 organization. CLK must be provided) after a start condition is detected. These clock cycles are required before all required opcodes, addresses, and data bits to execute the instruction. CLK and DI then become indifferent inputs waiting for a new start to detect the condition.

Program Enablement (PE)
This PIN allows the user to enable or disable this feature to write data to the memory array. If the PE pin is tied to VCC, the device can be programmed. If the PE pin is tied to VSS, programming will be disabled. Sports are not offered on the 93XX86A or 93XX86B. On these devices, programming is always enabled. This pin cannot float and must be tied to VCC or VSS