The ADS1240 and ADS1241 feature precision wide dynamic range, delta-sigma, analog-to-digital (A/D) converters with 24-bit resolution that operate from 2.7V to 5.25V. The delta-sigma A/D converter provides up to 24 bits of no missing code performance and an effective resolution of 21 bits. Input channels are multiplexed. Internal buffering can optionally provide very high input impedance sensors or low level voltage signals for direct connection. A burnout current source is provided to allow detection of open or shorted sensors. An 8-bit digital-to-analog converter (D/A) provides offset correction over a 50% full-scale range (FSR). Programmable Gain Amplifier (PGA) provides selectable gains of 1 to 128 , with an effective resolution of 19 bits and a gain of 128. A/D conversion is accomplished using a second-order delta-sigma modulator and a programmable finite impulse response (FIR) filter. Simultaneous 50Hz and 60Hz notch. The reference input is differential and can be used for ratio conversion. The serial interface is SPI compatible. Up to 8-bit data also provides I/O that can be used for input or output. The

The ADS1240 and ADS1241 are designed for smart transmitters, high-resolution measurement applications in industrial process control, weighing scales, chromatographs and portable instruments.

feature

24 codes that are not missing

Simultaneous 50Hz and 60Hz rejection (-90dB MINIMUM)

0.0015% INL

21 BITS valid solution (PGA = 1), 19 bits (PGA = 128)

PGA gain from 1 to 128

Single cycle sedimentation

Programmable data output rate

External differential reference 0.1V to 5V

On-chip calibration

SPI™ Compatible

2.7V to 5.25V supply range

600μW power consumption

Note the eight input channels

Up to 8 data I/Os.

Pin Configuration Diagram (ADS1240)

Pin Configuration Diagram (ADS1241)

Pin Description (ADS1240)

Number name description

1 DVDD digital power supply

2 DGND digital ground

3 XIN clock input

4 XOUT clock outputs for use with external crystals.

5 RESET Active low resets the entire device.

6 DSYNC active low, synchronization control

7 PDWN Active low, power down. The power-down function shuts down analog and digital circuits.

8 DGND digital ground

9 VREF + Positive Differential Reference Input

10 VREF - Negative Differential Reference Input

11 AIN0/D0 Analog Input 0/Data I/O 0

12 AIN1/D1 Analog Input 1/Data I/O 1

13 AIN2/D2 Analog Input 2/Data I/O 2

14 AIN3/D3 Analog Input 3/Data I/O 3

15 AINCOM Analog Input Common, if not used, connect to AGND.

16 AGND analog ground

17 AVDD analog power supply

18 POL Serial Clock Polarity

19 CS active low, chip select

20 DIN Serial Data Input, Schmitt Trigger

21 DOUT serial data output

22 SCLK serial clock, Schmitt trigger

23 DRDY active low, data ready

24 BUFEN Buffer Enable

Password Description (ADS1241)

Number name description

1 DVDD digital power supply

2 DGND digital ground

3 XIN clock input

4 XOUT clock outputs for use with external crystals.

5 RESET Active low resets the entire device.

6 DSYNC active low, synchronization control

7 PDWN Active low, power down. The power-down function shuts down analog and digital circuits.

8 DGND digital ground

9 VREF + Positive Differential Reference Input

10 VREF - Negative Differential Reference Input

11 AIN0/D0 Analog Input 0/Data I/O 0

12 AIN1/D1 Analog Input 1/Data I/O 1

13 AIN4/D4 Analog Input 4/Data I/O 4

14 AIN5/D5 Analog Input 5/Data I/O 5

15 AIN6/D6 Analog Input 6/Data I/O 6

16 AIN7/D7 Analog Input 7/Data I/O 7

17 AIN2/D2 Analog Input 2/Data I/O 2

18 AIN3/D3 Analog Input 3/Data I/O 3

19 AINCOM Analog Input Common, if not used, connect to AGND.

20 AGND analog ground

21 AVDD analog power supply

22 POL Serial Clock Polarity

23 CS active low, chip select

24 DIN Serial Data Input, Schmitt Trigger

25 DOUT serial data output

26 SCLK serial clock, Schmitt trigger

27 DRDY active low, data ready

28 BUFEN Buffer Enable

Timing Diagram 1

Timing Diagram 2

The input multiplexer provides any combination of differential inputs selected on any input channel, as shown in Figure 1. For example, if AIN0 is selected as the positive differential input channel, any other channel can be selected as the negative terminal channel of the differential input. Using this approach, there can be up to eight single-ended input channels or four independent differential input channels of the ADS1241 and four single-ended input channels or two independent differential input channels of the ADS1240. Note that AINCOM can be considered an input channel.

The ADS1240 and ADS1241 feature single-cycle stabilization digital filters that provide valid data on the first conversion after new channel selection. To minimize setup errors, MUX changes are synchronized to the start of a conversion, indicated by the falling edge of DRDY. exist

In other words, the MUX change is issued via WREG as soon as DRDY goes low and the command minimizes the resolution error. Increasing the time between conversions begins (DRDY goes low) and a MUX change command (tDELAY) results in the establishment of incorrect data in the conversions, as shown in Figure 2. Burnout current source Burnout current source can be used to detect sensor shorted or open circuit conditions. Setting the current source (BOCS) bits in the burnout SETUP register activates two 2µA current sources called burnout current sources. One current source is connected to the negative input of the converter and the other is connected to the positive input of the converter. Figure 3 shows the case of an open sensor. this

is a potential failure mode for many remotely connected sensors. The current source of the positive input acts as a pull-up, causing the positive input to go to the positive analog supply, and the negative input current source acts as a pull-down, causing the negative input to ground. Therefore, the ADS1240/41 outputs full scale (7FFFFF hex).

input buffer

The input impedance enable of the ADS1240/41 without the buffer is about 5MΩ/PGA. For systems requiring very high input impedance, the ADS1240/41 provide chopper-stabilized differential FET input voltage buffers. When activated, the buffer will boost the ADS1240/41 input impedance to approximately 5GΩ The input range of the buffer is approximately 50mV to AVDD - 1.5V. The linearity of the buffer will be reduced outside this range. The differential signal should be adjusted so that the two signals are evenly within the input range of the buffer. The BUFEN pin can be used or the BUFEN bit in the buffer ACR register can be enabled using BUFEN. The BUFEN pin is high and the BUFEN bit is set when the buffer is open. If the BUFEN pin is low, the buffer is disabled. If the BUFEN bit is set to zero, the buffer is also disabled.

The buffer consumes additional current when active. The current required by this buffer depends on the PGA settings. When the PGA is set to 1, the buffer uses about 50µA; when the PGA is set to 128, the buffer uses about 500µA. The PGA Programmable Gain Amplifier (PGA) can be set to gain 1, 2, 4, 8, 16, 32, 64 or 128. Using a PGA can improve the effective resolution of the A/D converter. For example, with a 5V full-scale signal with a PGA of 1, the A/D converter can step down to 1µV. The PGA is 128, the full scale number is 39mV, and the A/D converter can resolve down to 75nV. The current increases when AVDDPGA is set above 4. OFFSET DAC

The input of the PGA can be shifted by half the full-scale input of the PGA range using the Offset DAC (ODAC) register. The ODAC register is an 8-bit value; the MSB is the flag and the LSB provides the magnitude of the offset. Using an offset DAC will not degrade the performance of the A/D converter. For more details on ODAC, see TI filing report SBAA077 Modulator is a single-loop second-order system. This modulator runs the external clock (fOSC) at the clock speed (fMOD) of the source.

Both the ADS1240 and ADS1241 support self and system calibration. The self-calibration of the ADS1240 and ADS1241 corrects internal offset and gain errors and is handled by three commands: SELFCAL, SELFGAL, and SLEFOCAL. The SELFCAL command performs offset and gain calibration. SELFGCAL performs gain calibration and SELFOCAL performs offset calibration, each of which takes two tDATA cycles to complete. During self-calibration, the ADC input is internally disconnected from the input pins. The PGA must be set to 1 before issuing a SELFCAL or SELFGCAL command. PGA is allowed on any SELFOCAL command. For example, if using PGA=64, first set PGA=1 and issue.