The 82C89 is typically used in medium to large 80C86 or 80C88 systems where multiple processors must access the bus to coordinate. The 82C89 also offers high output current and capacitive drivers without additional bus buffering. Static CMOS circuit design ensures low power consumption. This advanced Intersil SAJI CMOS process achieves performance equal to or greater than existing equivalent products in significant power savings.

feature

Pin compatible with bipolar 8289

Performance Compatible:

Provides multi-master system bus control and arbitration

Provides simple interface regulator for 82C88/8288 bus

Synchronized multi-master bus using 80C86/8086, 80C88/8088 processors

Bipolar drive capability

Four operating modes for flexible system configuration

low power operation

Pin Diagram

functional map

Pin Description

Symbol Number Type Description

VCC 20 VCC: +5V power supply pin. A 0.1µF capacitor is recommended for decoupling between pins 10 and 20. GND 10 is grounded.

S0, S1, S2 1, 18-19 I Status Input Pins: Status input pins from an 80C86, 80C88 or 8089 processor. The 82C89 decodes these pins to initiate bus request and abort operations.

CLK 17 I Clock: From the 82C84A or 82C85 clock chip used to determine when to initiate bus arbiter operation.

LOCK 16 I LOCK: A processor-generated signal that, when asserted (low), prevents the arbiter from handing the multi-master system bus to any other bus arbiter, regardless of its priority.

CRQLCK 15 I COMMON REQUEST LOCK: Active low signal, prevents arbiter from giving up multi-master

The system bus to any other bus arbiter requests the bus through the CBRQ input pin.

RESB 4 I RESIDENT BUS: A bundling option for configuring the arbiter to operate in a system with multiple masters

System bus and resident bus. high-speed, multi-master system bus is required or surrendered to a

Function of the SYSB/RESB input pins. Hold low, the SYSB/RESB input is ignored.

ANYRQST 14 I ANY REQUEST: A bundling option that allows the multi-master system bus to be lowered to lower

The priority arbiter acts as if it were a higher priority arbiter (i.e., when a lower priority arbiter requests the use of that priority

multi-master system bus, the bus is handed over as soon as possible). When ANYRQST is tied low,

According to Table A in the design information, the bus is handed over. If ANYRQST is tied high and CBRQ is

When activated, the bus hands over at the end of the current bus cycle. Bundle CBRQ low and ANYRQST high

Forces the 82C89 arbiter to relinquish the multi-master system bus after each transfer cycle. Note that when

Surrender occurs when BREQ is driven false (high).

IOB 2 I IO BUS: Bundle option to configure the 82C89 Arbiter to operate in a system with an IO bus

(peripheral bus) and multi-master system bus. Arbiter requests and abandons the use of multi-master

The system bus is a function of the status line, S2. Allow Multi-Master System Bus Abandonment

The processor is executing IO commands and memory is being requested as long as the processor is executing

Order. It is assumed that the interrupt cycle comes from the peripheral bus and is treated as an IO command.

AEN 13 O ADDRESS ENABLE: The address output by the 82C89 Arbiter to the processor is latched into the 82C88 bus

controller and 82C84A or 82C85 clock generator. AEN is used to indicate the bus controller and address latch

When three state their output drivers.

INIT 6 I INITIALIZE: An active low multi-master system bus input signal used to reset all bus arbiters on the multi-master system bus. After initialization, no arbiter can use the multi-master system bus.

The 82C89 bus arbiter is used in conjunction with the 82C88 bus controller to connect the 80C86, 80C88 processors to the multi-master system bus (both the 80C86 and 80C88 are configured in their maximum mode). The processor is unaware that the arbiter exists and issues commands as if it had exclusive use of the system bus. If the processor is not using the multi-master system bus, the arbiter prevents the bus controller (82C88), data transceivers and address latches from accessing the system bus (eg all bus drivers) outputs are forced into a high impedance state. Since the command sequence was not issued by the 82C88 system the bus will show as "Not Ready" and the processor will enter a wait state. The processor will keep waiting until the bus arbiter gains use of the multi-master system bus and then the arbiter will allow the bus controller, data transceiver and address latches to access the system.

Typically, once a command has been issued and a data transfer has occurred, a transfer acknowledgement (XACK) is returned to the processor to indicate a "READY" access to the slave device. The processor then completes its branch cycle. Hence the arbiter is used to multiplex processors (or bus masters) onto a multi-master system bus and avoid contention problems between bus masters.

prioritizing technology

Since there can be many bus masters on a multi-master system bus, some method of resolving priority between buses must provide masters requesting the bus at the same time. The 82C89 bus arbiter provides several resolution techniques. All techniques are based on the concept of priority of a given time, one bus owner will take precedence over everyone else. There are prescribed techniques using parallel priority resolution, serial priority resolution techniques and rotational priority techniques.

Parallel Priority Resolution

The parallel priority resolution technique uses a separate bus request line to the BREQ bus for each arbiter on a multi-master system, and each BREQ line goes into a priority encoder which generates the binary address of the highest priority BREQ for the active line. The binary address is decoded by a

The decoder selects the corresponding BPRN (Bus Priority In) line to return to the highest priority request arbiter. This arbiter receives the priority (BPRN is true) and then allows its associated bus master to enter the multi-master system as soon as the bus becomes available (ie, the bus is no longer busy). When a bus arbiter takes precedence over another arbiter, it cannot grab the bus right away and must wait until the current bus transaction is complete. After completing the transaction the current bus passenger realizes that it no longer has priority and surrenders the bus by releasing the BUSY. BUSY is an active low-OR connection signal line connected to each bus arbiter system bus. When BUSY goes inactive (high), the arbiter currently has bus first (BPRN is true) then grabs the bus and pulls BUSY low to take the other arbiters off the bus. Note that all multi-master system bus transactions are synchronized to the bus clock (BCLK). This allows parallel priority resolution circuits or any other priority solution to resolve.

Parallel first solution technical diagram

Serial priority parsing

Serial priority resolution technology eliminates the need to use priority encoder-decoder arrangements through daisy-chaining Arrange bus arbiters together, connect the BPRO (Bus Priority Out) output of the bus arbiter with higher priority to BPRN with the next lower priority See below.

Which priority resolution technique to use each has advantages and disadvantages to the above techniques. The rotary priority resolution technique requires a lot of external logic to implement the serial technique that does not use external logic but can accommodate only a limited number of bus arbitrators until the daisy-chain propagation delay exceeds the multi-master system bus clock (BCLK). Parallel priority resolution techniques are usually a compromise between the other two techniques. It allows many arbiters to appear on the bus although it doesn't require much logic to implement.

82C89 operating mode

The 82C89 has two types of processors

Provides support: input/output processor (ie NMOS8089 IOP) and 80C86, 80C88. Therefore, there are two basic modes of operation of the 82C89 bus arbiter. One, IOB (I/O Peripheral Bus) mode, which allows the processor to access the I/O peripheral bus and the multi-master system bus. The second, RESB (Resident Bus Mode) allows the processor to communicate via the Resident Bus and a multi-master system bus. An I/O peripheral bus is a bus that all devices (including memory) on this bus are considered I/O. Devices and are addressed by I/O commands. All memory commands are directed to another bus, the multi-master system bus. The resident bus can issue memory and I/O. commands, but it is a separate bus from the multi-master system bus. The difference is that the resident bus has only one master, offering complete availability and presence dedicated to that master. The IOB bundle option configures the 82C89 bus arbiter to enter IOB mode, and the bundle option RESB configures it to enter RESB mode. It may be noted at this point that the arbiter interface processor can only interface to the multimaster bus if both have the bundle option is false. Both options are true, the arbiter interfaces the processor to a multi-master bus, a resident bus and an I/O bus. In IOB mode, the processor communicates and controls a peripheral host on a peripheral bus. When I/O. The processor needs to communicate with the system memory so through the system memory bus, the processor system is configured.

The 80C86 and 80C88 processors can communicate with a resident bus and a multi-master system bus. Two bus controllers require only one bus arbiter for a configuration as shown in Figure 6. Configuring the processor in such a system can access memory and peripherals on both buses. Memory mapping techniques are used to select which bus to access. The SYSB/RESB input on this arbiter is used to indicate to the arbiter whether or not to access the system bus. This signal connected to SYSB/RESB can also enable or disable commands from one of the bus controllers. Summarize the modes the 82C89 has, and line input in response to their states.

Typical Medium Complexity CPU System Diagram

Typical medium complexity IOB system

82C89 bus arbitration-resident bus configuration diagram shown in the system