HCPL-261A Series Optics This data shows that coupled gate slices provide all the benefits of the industry standard 6N137 series with the benefits of HCMOS compatible input currents. This therefore works directly with all common circuit topologies without additional LED buffer or driver components. The AlGaAs LED allows the use of lower drive currents and reduces degradation by using the latest LED technology. For mono components, the enable output allows the detector to be gated. The output IC of this detector is an open collector schottky-clamp transistor. Internal shrouds provide a minimum common mode transient immunity of 1000V/µs for the HCPL-261A family and 15000V/µs for the HCPL-261N series.

figure 1

Application Information

Common Mode Rejection Ratio for the HCPL-261A/HCPL-261N Family: Figure 1 shows the best common mode rejection performance when recommending a patched driver circuit for the HCPL-261N/-261A. Two points worth noting: 1. The enable pin is tied to VCC and not floating (this applies to the mono part only). 2. Two LED current setting resistors in place of 1. This is to balance out the ILED synchrony-variant mode transients. If the ENABLE pin is left floating, it is possible for a common-mode transient to couple into the ENABLE pin, resulting in a common-mode failure. This failure mechanism is only when the LED is lit and the output is in the low state. It is determined to be present when the instantaneous output voltage rises above 0.8V. Therefore, the enable pin should be tied to VCC or logic high for best common mode with output low performance (CMRL). This failure mechanism only exists for single channel accessories (HCPL-261N, -261A, -061N, -061A), which have an enable function. Additionally, common mode transients can be capacitively coupled from the anode (or cathode) output side of the LED to ground so that current is shunted away from the LED (which can be bad if the LED is on) or the opposite causes current to be injected into the LED ( bad if the LED is meant to be off). Figure 2 shows the parasitic capacitance that exists between the LED's anode/cathode and output ground (CLA and CLC). It also shows that the input side on Figure 2 is an AC equivalent circuit. Table 1 shows that the direction of I LP and ILN flow depends on the direction of the common mode transient. For the moment the LED turns on, the common-mode rejec- ization (CMRL, since the output is in the "low" state) depends on the number of LED current drivers (IF). For conditions where I F is close to the switching threshold (I TH), CMRL also depends on the degree I LP I LN balance and so on. In other words, an instantaneous reduction in IF caused by a common-mode transient at any state (ie, when dVCM/dt > 0 and |IFP| > |IFN|, see Table 1), will result in a common-mode fault as a transient which is not fast enough. Likewise, for common mode transients that occur when the LED turns off (ie CMRH, since the output is "high"), if the unbalanced ILP I LN results in an instant I F equal to or greater than the switching threshold of the optocoupler , transient "signals" can cause the output to spike below 2 V (which consti-tutes a CMRH failure). Using the recommended circuit shown in Figure 1, good CMR can be achieved. (If it is in the -261N family, a minimum of 15 kV CMR/µs is guaranteed to use this circuit.) Balanced ILED- Setting resistors helps balance ILP I LN by reducing the amount by I LED from modulation to C transient coupling LA and CLC .

figure 2

image 3

Table 1

CMR and other driver circuits

The CMR performance compared to the other driver circuits shown in Figure 1 can be improved by following these principles: 1. Use the driver circuit to shunt the current from the LED "off" status indicator (as in Figures 3 and 4) as indicated by Show. This is good for good CMRH.2. Use my FH > 3.5mA. This is good for high CMRL. Using any of the drivers in Figures 3-5 with circuits IF = 10mA will result in a typical 8kV CMR/µs time for the HCPL-261N family, as long as the PC board layout is practiced is next. Figure 3 shows a circuit that can be used with any totem pole output TTL/LSTTL/HCMOS logic gate. The buffered PNP transistors allow for low current-device sinking capability to be used with logic circuits. It also helps maintain the drive gate power-up supply current at a constant level minimizing ground transitions connected to other device input supply grounds. When using an open-collector TTL or open-drain output CMOS logic gate, the circuit shown in May 23 is used. When using CMOS gate drive optocouplers, the circuit shown in Figure 5 can be used. Parallel diodes use RLED to speed off optocoupler LEDs.

Figure 4

Figure 5