The C8051 F020/C8051F021/C8051F022/C8051F023 devices are fully integrated mixed-signal system-on-chip MCUs with 64 digital I/O pins

(C8051F020/C8051F022) or 32 digital I/O pins (C8051F021/C8051F023). Selection of specific product features.

High-speed pipelined 8051 compatible CIP-51 microcontroller core (up to 25 MIPS)

In-system, full-speed, non-intrusive debug interface (on-chip)

True 12-bit (C8051F020/C8051F021) or 10-bit (C8051F022/C8051F023) 100ksps 8-channel ADC with PGA and analog multiplexer

True 8-bit ADC500ksps 8-channel ADC with PGA and analog multiplexer

Two 12-bit DACs with programmable update scheduling

64k bytes of in-system programmable FLASH memory

4352 (4096+256) bytes of on-chip RAM

External data memory interface with 64kbyte address space

SPI, SMBus/I2C and (2) UART serial interfaces implemented in hardware

Five general-purpose 16-bit timers

Programmable counter/timer array with five capture/compare modules

On-chip watchdog timer, VDD monitor and temperature sensor

With an on-chip VDD monitor, watchdog timer and clock oscillator, the C8051F020/C8051F021/C8051F022/C8051F023 devices are true stand-alone system-on-system solutions. All analog and digital peripherals are enabled/disabled and configured by the user firmware. FLASH memory can even be reprogrammed in-circuit, providing non-volatile data storage and allowing field upgrades of the 8051 firmware. Onboard JTAG debug circuitry allows non-intrusive (without using on-chip resources), full-speed, in-circuit debugging using the production MCU installed in the final application. This debug system supports inspecting and modifying memory and registers, setting breakpoints, watchpoints, single stepping, run and pause commands. All analog and digital peripherals are fully functional when debugging using JTAG. Each MCU is rated to operate over a temperature range of 2.7 V to 3.6 V and an operating temperature range of -45°C to +85°C. The port I/O, /RST and JTAG pins can tolerate input signals up to 5V. The C8051F020/C8051F022 uses 100 pins.

C8051F020 block diagram

C8051F021 block diagram

C8051F022 block diagram

C8051F023 block diagram

The C8051F020 family uses Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The core has all the peripherals included in the standard 8052, including five 16-bit counters/timers, two full-duplex UARTs, 256 bytes of internal RAM, 128 bytes of Special Function Register (SFR) address space and 8/4 words Section-wide I/O ports.

The CIP-51 adopts a pipelined architecture, which greatly improves the instruction throughput compared to the standard 8051

architecture. In the standard 8051, all instructions except MUL and DIV require 12 or 24 system clock cycles to execute with a maximum system clock of 12 to 24 MHz. In contrast, the CIP-51 core executes 70% of the instructions

One or two system clock cycles, only four instructions take more than four system clock cycles. CIP-51 has a total of 109 instructions. The table below shows the total instruction count execution time processing time for each instruction.

The C8051F020 MCU family includes several key enhancements to the CIP-51 core and peripherals that improve the overall performance and ease of use of the end application. The extended interrupt handler provides 22 interrupt sources for the CIP-51 (compared to 7 for the standard 8051), allowing numerous analog and digital peripheral interrupt controllers. Interrupt-driven systems require less MCU intervention, making them more efficient throughput. Additional interrupt sources are useful for building multitasking, real-time systems.

The MCU has up to seven reset sources: an onboard VDD monitor, a watchdog timer, a lost clock

Detector, Comparator0 Voltage Level Detection, Forced Software Reset, CNVSTR Input Pin and /RST

pin. The /RST pin is bidirectional and can accommodate an external reset, or allow an internally generated POR

output on the /RST pin. Every reset source can be disabled except the VDD monitor and reset input pins

User in software; enable/disable VDD monitor via MONEN pin. The watchdog timer can be permanently enabled in software after a power-on reset during MCU initialization.

The MCU has an internal independent clock generator which by default is used as the system clock after any reset. if

The expectation is that the clock source can be switched on the fly to an external oscillator, which can use a crystal, ceramic resonator, capacitor, RC, or an external clock source to generate the system clock. This is very useful at low power

application that allows the MCU to run from a slow (power saving) external crystal source while periodically switching to the fast (up to 16 MHz) internal oscillator as needed.

Onboard Clock and Reset Diagram

The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with

The upper 128 bytes are double mapped. Indirect addressing accesses the upper 128 bytes of general-purpose RAM and points to direct addressing

Addressing accesses the 128-byte SFR address space. The lower 128 bytes of RAM are accessible through direct and indirect addressing. The first 32 bytes are addressable as 4 sets of general purpose registers, the next 16 bytes can be byte addressable or bit addressable.

The CIP-51 in the C8051F020/C8051F0201/C8051F0202/C8051F0203MCU also has an on-chip 4kbyte RAM module and external memory

Interface (EMIF) for accessing off-chip data memory. On-chip 4k byte blocks can be addressed over the entire 64k

External data memory address range (overlapping 4k boundaries). The external data memory address space can be

Mapped to on-chip memory only, off-chip memory only, or a combination of both (addresses up to 4k point to

On-chip, above 4k points to EMIF). EMIF can also be configured for multiplexed or non-multiplexed address/data

Wire.

The program memory of the MCU consists of 64k bytes of FLASH. This memory can be reprogrammed in the system

512 -byte sectors without special off-chip programming voltages. 512 bytes from address 0xFE00 to

0xFFFF is reserved for factory use. There is also a 128-byte sector at addresses 0x10000 to 0x1007F, where

A small table that can be used as a software constant. See the figure below for the MCU system memory map.

The C8051F020 series features on-chip JTAG boundary scan and debug circuitry to provide non-intrusive, full-speed,

In-circuit debugging is performed via the four-pin JTAG interface using the production part installed in the final application. Should

The JTAG port is fully IEEE 1149.1 compliant and provides full boundary scan for testing and manufacturing purposes.

Silicon Labs' debug system supports inspection and modification of memory and registers, breakpoints, watchpoints, stack monitors and single stepping. No additional target RAM, program memory, timers or communications

Channels are required. All digital and analog peripherals are functional and will work when debugging. all

Peripherals (except ADC and SMBus) stop working when the MCU is stopped, single-stepped, or in the execute state

breakpoints to keep them in sync.

The C8051F020DK development kit provides all the hardware and software required to develop application code

And use C8051F020/1/2/3 MCU for online debugging. The kit includes software with developer studio and debugger, integrated 8051 assembler and RS-232 to JTAG serial adapter. It also has a target application

A board with the associated MCU installed, RS-232 and JTAG cables, and a wall mount power supply. Should

The development kit requires a Windows 95/98/NT/ME/2000 computer and an available RS-232 serial port. as the picture shows

In the image below, the PC is connected to the serial adapter via RS-232. A 6" ribbon cable to Serial

The adapter connects to the user's application board, picking up the four JTAG pins and VDD and GND. Serial adapter required

Power from the application board; it requires about 20 mA at 2.7-3.6 V. For applications where the target system does not have enough power, the supplied power can be connected directly to the serial

adapter.

Compared to standard MCU emulators that use an on-board "ICE chip" and target cable and require an MCU, Silicon Labs' debug environment is an extremely superior configuration for developing and debugging embedded applications on the application board to be socketed. Silicon Labs' debug environment increases ease-of-use while preserving the performance of precision analog peripherals.