The DS2165Q ADPCM processor chip is a dedicated digital signal processing (DSP) chip that has been optimized to perform Adaptive Differential Pulse Code Modulation (ADPCM) voice compression at 3 different rates. The chip can be programmed to compress (extend) 64kbps voice data down to (from) either 32kbps, 24kbps, or 16kbps. 32kbps compression follows the algorithmic recommendations specified by CCITT G. 721 (July 1986) and the ANSIT 1.301 document (April 1987). Compressed to 24kbps compliant ANSIT1.303 files. The following proprietary algorithm, compressed to 16kbps, was developed by Dallas Semiconductor. The DS2165Q can switch compression algorithms on the fly. This allows users to maximize the use of available bandwidth on a dynamic basis.

figure 1

Overview

The DS2165Q consists of three main functional blocks: a high performance (10MIPS) DSP engine, two independent PCM interfaces (X and Y) directly connected to the serial time division multiplexing (TDM) backplane and a serial port that can Via an instant device configured on an external controller. A 10MHz master clock is required by the DSP engine. The DS2165Q can be configured to perform two expansions, 2 compressions, or one expansion and one compression. The data rates supported on the PCM/ADPCM data interface are from 256KHz to 4.096MHz. Typically, the PCM data rate is 1.544MHz for M-law and 2.048MHz for A-law. The device samples serially input PCM or ADPCM bitstreams in each channel in a user-programmed input slot, processes data in a user-programmed output slot, and outputs its result in a user-programmed output slot. Each PCM interface has a control register that specifies functional characteristics (compression, expansion, bypass and idle), data format (M-law or A-law) and algorithm reset control. With SPS tied high, software mode is enabled and the serial port can be used to configure the device. In this mode, a new solution allows multiple devices to share a 3-wire control bus, simplifying system-level interconnection. With SPS low, hardware mode is enabled. This mode disables the serial port mapping and certain control register bits for some address and serial port pins. In hardware mode, no external host is required for the controller and all PCM/ADPCM input and output time slots default to 0 time slots.

hardware reset

RST allows the user to reset the algorithm and the contents of the internal registers for both channels. This pin must be held low for at least 1ms stable after the main clock on system power-up to ensure that the device has initialized properly. Mode should also be set when RST is changed or from hardware. RST clears both channels of the control register, except for all bits of the IPD bit; the interpupillary distance bit is set to 1 for both channels.

software mode

Connecting SPS high enables software mode. In this mode, the external host controller writes the DS2165Q through the input SCLK, SDI and configuration data through the serial port CS (Figure 2). Each write to the DS2165Q can be a 2-byte write or a 4-byte write. A 2-byte operation consists of the address/command byte (ACB), followed by a byte to configure the control register (CR) for either the X or Y channel. 4 bytes are written by ACB, followed by one byte to configure the CR, then 1 byte to set the input slot and another byte to set the output slot.

figure 2

control register

Control registers determine idle, algorithm reset, bypass, data format, and channel coding for the selected channel. The PCM interface on the X-side and Y-side can be independently disabled (output tri-stated) with interpupillary distance. When the IPD sets both channels, the device enters a low-power standby mode. In this mode, the serial port cannot operate faster than 39kHz. ALRST resets the selected channel to the initial value of the algorithm coefficients. ALRST is cleared by the device when the algorithm is reset upon completion.

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