Features selectable watchdog timer
- Select 200ms , 600ms , 1.4s, off low VCC detection and reset assert
- Five standard reset threshold voltages rated 4.62V, 4.38V, 2.92V, 2.68V, 1.75V
- Use a special programming sequence to adjust the low VCC reset threshold voltage
-Reset signal valid until VCC=1V
Low power CMOS
-12µA typical standby current with watchdog on
-800NA typical standby current watchdog off
-3ma active current
400kHz I2c interface
1.8V to 5.5V Power Supply Operation Available in Software Packages
-8-lead SOIC
-8 lead MSOP
Description These devices combine three common functions: power reset control, watchdog timer, and supply voltage.
Supervision. This combination reduces system cost, reduces board space requirements, and increases reliability.
Applying power to the device activates the power supply.
The reset circuit segment time to make reset/reset active. This allows the power supply and oscillator to stabilize before the processor executes code.
A watchdog timer provides a microcontroller-independent protection mechanism. When the microcontroller fails to restart the timer within a selectable timeout interval, the device initiates a reset. reset signal. The user selects the interval preset from three options. Once selected, the interval does not change, even after cycling the power.
The device's low VCC detection circuit protects the user's system from low voltage conditions, resetting the system point when VCC falls below the minimum VCC trip. reset/reset is asserted until VCC returns to the proper operating level and stabilizes. Five industry-standard vtrip thresholds are provided; however, Cicco's unique circuitry allows the thresholds to be reprogrammed to meet custom requirements, or fine-tuned for applications requiring higher accuracy.

Principle of Operation Power-on reset Powering up the X4003 /X4005 activates the power-on reset circuit, pulling the reset/reset pin active. This signal provides several benefits.
– Prevents the system microprocessor from starting to work under low voltage conditions.
– It prevents the processor from stabilizing the oscillator.
– It allows the FPGA to download its configuration before the circuit is initialized.
When VCC exceeds the device vtrip threshold for 200ms (nominal), the circuit releases reset/reset, allowing the system to begin operation.
During low voltage monitoring operation, X4003/X4005 monitors VCC level and asserts reset/reset if the supply voltage drops below a preset minimum vtrip. The reset/reset signal prevents the microprocessor during a power outage or blackout

The VCC returns and exceeds the vertical takeoff 200ms.
Watchdog Timer The watchdog timer circuit monitors the activity of the microprocessor by monitoring the sda and scl pins. This microprocessor must toggle the SDA pin from high to low.
Periodically, SCL also toggles from high to low.
(this is a start bit) and then the watchdog timeout period expires to prevent the reset/reset signal. The state of two nonvolatile control bits in the control register determines the watchdog timer period. The microprocessor can change these watchdog bits, otherwise they could be "locked up" by tying the WP pin high

CC Threshold Reset Procedure
The X4003/X4005 ships with a standard VCC threshold (vtrip) voltage. This value will not change beyond normal operating and storage conditions. However, in standard vtrips it is not entirely correct, or if higher precision vtrip values are required, the x4003/x4005 thresholds may be adjusted. The procedure is described below and uses the application of non-volatile control signals.
Setting the vtrip voltage This procedure is used to set the vtrip to a higher voltage value. For example, if the current vtrip is 4.4V and the new vtrip is 4.6V, this program will make the change directly. If the new setting is lower than the current setting, then it is necessary to reset the trip point before setting the new value.

To set a new vtrip voltage, apply the desired vtrip threshold voltage to the VCC pin and connect the WP pin to the programming voltage Vp. Then write data 00HTO to address 01H. The stop bit after a valid write operation initiates the vtrip programming sequence. Bring wp low to complete the operation.
Reset vtrip voltage This procedure is used to set the vtrip to the "native" voltage level. For example, if the current vtrip is 4.4V the new vtrip must be 4.0V, then the vtrip must be reset. When resetting the vtrip, the new vtrip is less than 1.7V. This procedure must be used to set the voltage to a lower value.
To reset the new vtrip voltage, apply the desired vTrip threshold voltage to the VCC pin and tie the WP programming voltage to the vp pin. Then write 00h to address 03H. The stop bit for a valid write operation initiates the vtrip programming sequence. Bring wp low to complete the operation.

Control Register The control register provides the user with changing watchdog timer settings. The watchdog timer bits are nonvolatile when power is removed.
The control register is accessed via a special preamble in the slave byte ( 1011 ) and is located at the address.
1FFH. It can only be modified by executing control register write operations. Only one data byte is allowed for each register write. In writing to the control register, the WEL and RWEL bits must be set using a two-step process, the entire process requires 3 steps. See "Writing to Control Registers" below.
The user must issue a stop register byte after sending control, which is used to initiate a non-volatile loop storing WD1 and WD0. The X4003/X4005 will not acknowledge that any data bytes written after the first byte have been entered.

The state of the control register is available at any time a serial read operation is performed. Only one byte is read by each register read operation. After this reads the first byte, the x4003/x4005 resets itself. The host shall provide a stop condition consistent with the bus protocol, but a stop is not required to end this operation.
Register Write Enable Latch (volatile) The RWEL bit must be set to '1' before writing to the control register.
WEL: Write Enable Latch (volatile) The WEL bit controls access to the control register during a write operation. This bit is a volatile latch that powers up in the low (disabled) state. When the world bit is low, writes to the control register are ignored (no acknowledgment is issued after a data byte).
The WEL bit is set by writing a "1" to the WEL bit, and
0 to other bits in the control register. Once set, WEL remains set until it resets to 0 (by writing '0' to the WEL bit and 0 to the other bit control registers) or until the part is powered up again.
Writing the WEL bit does not cause a nonvolatile write cycle, making the device ready for the next operation immediately after the STOP state.
WD1, WD0: Watchdog Timer Bits WD1 and WD0 control the period of the watchdog timer. The options are shown below.
Writing to the control register changes any non-volatile bit of the control register requires the following steps:
– Write 02h to the control register to set the write.
Enable Latch (WEL). This is a volatile operation, so there is no delay after writing. (Operation starts and then stops.) – Write 06h to the control register to set the register write enable latch (RWEL) and the WEL bit.
It's also an unstable cycle. Zero bytes in the data are required. (The operation before starting is finally stopped.)
– Write a value to a control register that has control bits set to the desired state. This can be represented in binary as 0xY0 0010, where xy are the WD bits. (There is a start and end before the operation. Because this is a non-volatile write cycle, it takes 10ms to complete. The RWEL bit is reset through this cycle, and the sequence must be repeated to change the non-volatile bits again. If the first Bit 2 is set to '1' in the third step (0xY0 0110), then the RWEL bit is set, but the WD1 and WD0 bits remain unchanged. Writing the second byte to the control register is not allowed. Doing so will abort Write operation and return a nack.
– Read operations that occur between any previous operations do not interrupt register writes.
operate.
– If you do not write to the non-volatile control bits in the control register, power cycle the device or attempt to write to the protected block.
For example, a device write sequence consisting of [02h, 06h, 02h] will reset the bits in all nonvolatile control registers to 0. A series of [02h, 06h, 06h] will leave the non-volatile bits unchanged and the RWEL bit will remain set.
Serial Interface Serial Interface Conventions This device supports a bidirectional bus-oriented protocol. The protocol defines any device that sends data on the bus as a transmitter and a receiving device as a receiver. The device that controls the transfer is called the master, and the controlled device is called the slave. The host always initiates data transfers, and operates for transmit and receive. Therefore, devices of this family operate as slave servers in all applications.
The data state on the serial clock and data sda lines can only be low on SCL. The SDA state change while SCL is high is used to indicate start and stop conditions.

Valid Data Change Data Stable Data Change Data Stable on the SDA bus Serial Start Condition All commands are preceded by a Start condition when SCL is high. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any commands until this condition is met. See Serial Stop Condition All communications must be terminated by a stop condition, which is a low-to-high transition of SDA when SCL is high. A STOP condition is also used to place the device into the standby power mode sequence after reading. A STOP condition can only be used when the transmitting device has released the bus.
Valid start and stop conditions start-stop serial acknowledgments are used to indicate successful data transfer. The transmitter, or master-slave, releases the bus eight bits after sending. During the ninth clock cycle, the receiver will pull the SDA line low to acknowledge receipt

Serial Write Operation Slave Address Byte After a Start condition, the master must output the slave address byte. This byte consists of several parts: – Device type identifier which is always "1011".
– 2 bits “0” – one bit from the command byte is the R/W bit. The r/w bits of this slave address byte define the operation to be performed. When the R/W bit is 1, a read operation has been selected. Zero-select write operations.
– From the SDA bus, the device compares the incoming slave byte data to the correct slave byte. After a proper comparison, the device outputs a confirmation line on sda.
Writing to the Control Register To write to the control register, the device needs a slave address byte and a byte address. This gives the main access register. After receiving the address byte, the device responds with an acknowledgment, and waits for data. After receiving 8 bytes of data, the device responds again with an acknowledgment.
The master then generates a STOP state, at which point the device begins an internal write cycle to the non-volatile memory. During this internal write cycle, the device input is disabled, so the device will not respond from the master. If wp is high, the control register cannot be changed. A write to the control register will disable the acknowledge bit in the control register and no data will be changed. With wp low, a second byte write to the control register terminates the operation and no write occurs.
STOP AND WRITE MODES A STOP condition to terminate a write operation must be sent by the host after sending 1 complete data byte plus a subsequent acknowledgment. If the associated ACK is sent in the middle of a data byte, or before 1 full data byte plus, then the device will reset not to perform a write operation.

Serial Read Operation The read operation allows the host to access the control register. Compliant with the I2C standard R/W bit set to 1 for slave address bytes prior to release, the master must first perform a "dummy" write operation. The master issues a start condition and a slave address byte, receives an acknowledgement, and then issues the byte address. Upon acknowledging receipt of the byte address, the master immediately issues another START condition and the slave address byte with the R/W bit set to 1. This is followed by an acknowledgment from the device again controlled by an eight-bit control register.
The master acknowledges the response by not terminating the read operation, and then issues a stop condition.
Acknowledgment and data transfer sequence.
Operating Instructions The device is powered up in the following states: – The device is in a low power standby state.
The –WEL bit is set to '0'. In this state it is impossible to write to the device.
– SDA pin is input mode.
The reset/reset signal is valid for t-explosion.

Data protection includes the following circuits to prevent accidental writes by the X4003/X4005CPU supervisor:
The –WEL bit must be set to allow write operations.
– Requires correct clock count and bit sequence.
A nonvolatile write cycle is initiated before the stop bit.
– A three-step sequence is required to change the watchdog timer or block lock settings before writing.
– When holding the WP pin high, all writes to the control register are blocked.
– Communication with the device is inhibited below the V trigger voltage.
– When reset/reset is active, the command to change the control register will terminate if it is in progress.